ISO150AP datasheet(9/21 Pages) TI1

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LOGIC LEVELS

PROPAGATION DELAY AND SKEW

POWER SUPPLY

MODE CHANGES

STANDBY MODE

POWER-UP STATE

CIRCUIT LAYOUT

SIGNAL LOSS

ISO150

www.ti.com .......................................................................................................................................... SBOS032D – SEPTEMBER 2000 – REVISED AUGUST 2008

Still, some applications with large, noisy isolation-

mode voltage can produce data errors by causing the

receiver output to change states. After a data error,

A single pin serves as a data input or output,

subsequent changes in input data will produce correct

depending on the mode selected. Logic inputs are

output data.

CMOS with thresholds set for TTL compatibility. The

logic threshold is approximately 1.3 V with 5 V

supplies with approximately 400 mV of hysteresis.

Input logic thresholds vary with the power-supply

Logic transitions are delayed approximately 27ns

voltage. Drive the logic inputs with signals that swing

through the ISO150. Some applications are sensitive

the full logic voltage swing, note that the ISO150 will

to data skew—the difference in propagation delay

use somewhat greater quiescent current if logic

between channel 1 and channel 2. Skew is less than

inputs do not swing within 0.5 V of the power-supply

2ns between channel 1 and channel 2. Applications

rails.

using

than

one

ISO150

must

allow

for

In receive mode, the data output can drive 15

somewhat greater skew from device to device. As all

standard LS-TTL loads. It will also drive CMOS loads.

devices are tested for delay times of 20ns min to

The output drive circuits are CMOS.

40ns max, 20ns is the largest device-to-device data

skew.

Separate, isolated power supplies must be connected

to side A and side B to provide galvanic isolation.

The transmission direction of a channel can be

Nominal rated supply voltage is 5 V. Operation

changed on the fly by reversing the logic levels at the

extends from 3 V to 5.5 V. Power supplies should be

channel's R/T pin. Note that when channel direction is

bypassed close to the device pins on both sides of

changed,

the

output

state

the

channel

the isolation barrier.

indeterminate (either high or low) and cannot be

known until an input signal is applied. The output

The VS pin for each side powers the transceivers for

begins to track the input as soon as the input

both channel 1 and 2. The specified supply current is

receives a change in logic state, either low to high or

the total of both transceivers on one side, both

high to low.

operating in the indicated mode. Supply current for

one transceiver in transmit mode and one in receive

mode

can

estimated

averaging

the

specifications for transmit and receive operation.

Quiescent current of each transceiver circuit is very

Supply current varies with the data transmission rate

low in transmit mode when input data is not changing

— see the typical characteristics.

(1nA

typical).

conserve

power

when

data

transmission is not required, program both side A and

B transceivers for transmit mode. Input data applied

to either transceiver is ignored by the other side.

When the device is powered up or direction is

High-speed data applied to either transceiver will

changed, the transceiver output is indeterminate

increase quiescent current.

(either high or low) and cannot be known until an

input signal is applied. The output begins to track the

input as soon as the input receives a change in logic

state, either low to high or high to low.

The high speed of the ISO150 and its isolation barrier

require careful circuit layout. Use good high speed

logic layout techniques for the input and output data

lines. Power supplies should be bypassed close to

The ISO150's differential-mode signal transmission

the device pins on both sides of the isolation barrier.

and careful receiver design make it highly immune to

Use low inductance connections. Ground planes are

voltage across the isolation barrier (isolation-mode

recommended.

voltage). Rapidly changing isolation-mode voltage

can cause data errors. As the rate of change of

Maintain spacing between side 1 and side 2 circuitry

isolation voltage is increased, there is a very sudden

equal or greater than the spacing between the

increase in data errors. Approximately 50% of all

missing pins of the ISO150 (approximately 7mm).

ISO150s will begin to produce data errors with

isolation-mode transients of 1.6kV/

µs. This may occur

as low as 500 V/

µs in some devices. In comparison,

a 1000 Vrms, 60 Hz isolation-mode voltage has a

rate of change of approximately 0.5V/

µs.

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