LM1247 datasheet(39/48 Pages) NSC

39 / 48 page

Pre-Amplifier Interface Registers (Continued)

Bits 7–0

This register determines the output of DAC 3. The full-scale output is determined by bit 5 of the

DAC Config, OSD Contrast & DC Offset Register (0x8438).

DAC 4 Output Level:

DAC4CTRL (0x8437)

DAC 4 Output Level

BA[7:0]

Bits 7–0

This register determines the output of DAC 4. The output of this DAC can be scaled and mixed

with the outputs of DACs 1–3 as determined by bit 6 of the DAC Config, OSD Contrast & DC

Offset Register.

DAC Config, OSD Contrast & DC Offset:

DACOSDDCOFF (0x8438)

Res’d

DAC Options

OSD Contrast

DC Offset

DCF[1:0]

OSD[1:0]

DC[2:0]

Bits 2–0

These determine the DC offset of the three video outputs, blue, red and green.

Bits 4–3

These determine the contrast of the internally generated OSD.

Bit 5

When this bit is a 0, the full-scale outputs of DACs 1–3 are 0.5V to 4.5V. When it isa1the

full-scale level is 0.5V to 2.5V.

Bit 6

When this bit is a 0, the DAC 4 output is independent. When it is a 1, the DAC 4 output is scaled

by 50% and added to the outputs of DACs 1–3.

Bit 7

Reserved and should be set to zero.

Global Video Control:

GLOBALCTRL (0x8439)

Reserved

Power

Blank

XXXXX

Bit 0

When this bit is a 1, the video outputs are blanked (set to black level). When it is a 0, video is not

blanked.

Bit 1

When this bit is a 1, the analog sections of the preamplifier are shut down for low power

consumption. When it is a 0, the analog sections are enabled.

Bits 7–2

Reserved and should be set to 0.

Auxillary Control:

AUXCTRL (0x843A)

Reserved

Int Clp

H Blnk

XXXXX

ACEn

HBEn

Bit 0

When this bit is a 1, the horizontal blanking input at pin 24 is gated to the video outputs to provide

horizontal blanking. When it is a 0, the horizontal blanking at the outputs is disabled.

Bit 1

When this bit is a 1, the internal auxillary clamp is enabled. This operates on the blue video input

so that if its level falls below 0.8 VDC, then this turns the internal clamp on to raise the output

level. This is not to be confused with the black level video clamp in the next register (0x843E).

Bit 2

This bit is reserved and should be set to a 1.

Bits 3–7

These bits are reserved and should be set to 0.

PLL Range:

PLLFREQRNG (0x843E)

Reserved

Clamp

OSD

VBlank

PLL

CLMP

OOR

VBL

PFR[1:0]

LM1247 Datasheet(PDF) 39 Page - National Semiconductor (TI)

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