LPC47N267 datasheet(4/180 Pages) SMSC

4 / 180 page

SMSC DS – LPC47N267

Page 4

Rev. 10/23/2000

TABLE OF CONTENTS

FEATURES....................................................................................................................................................................1

GENERAL DESCRIPTION ............................................................................................................................................3

1.0

PIN LAYOUT.......................................................................................................................................................6

2.0

PINOUT –STQFP................................................................................................................................................7

3.0

PIN DESCRIPTION.............................................................................................................................................8

3.1

BUFFER TYPE DESCRIPTION ..............................................................................................................................15

3.2

PINS THAT REQUIRE EXTERNAL PULLUP RESISTORS............................................................................................15

4.0

BLOCK DIAGRAM ...........................................................................................................................................16

5.0

3.3 VOLT OPERATION / 5 VOLT TOLERANCE..............................................................................................17

6.0

POWER FUNCTIONALITY ...............................................................................................................................17

6.1

VCC POWER ...................................................................................................................................................17

6.2

VTR SUPPORT.................................................................................................................................................17

6.3

INTERNAL PWRGOOD.....................................................................................................................................17

6.4

TRICKLE POWER FUNCTIONALITY .......................................................................................................................17

6.5

MAXIMUM CURRENT VALUES .............................................................................................................................18

6.6

POWER MANAGEMENT EVENTS (PME/SCI) ........................................................................................................18

7.0

FUNCTIONAL DESCRIPTION..........................................................................................................................19

7.1

SUPER I/O REGISTERS......................................................................................................................................19

7.2

HOST PROCESSOR INTERFACE (LPC) ................................................................................................................19

7.3

LPC INTERFACE ...............................................................................................................................................19

8.0

FLOPPY DISK CONTROLLER.........................................................................................................................23

8.1

FDC INTERNAL REGISTERS ...............................................................................................................................23

8.2

STATUS REGISTER ENCODING ...........................................................................................................................34

8.3

DMA TRANSFERS.............................................................................................................................................36

8.4

CONTROLLER PHASES.......................................................................................................................................36

8.5

COMMAND SET/DESCRIPTIONS ..........................................................................................................................37

8.6

INSTRUCTION SET.............................................................................................................................................40

8.7

DATA TRANSFER COMMANDS.............................................................................................................................47

8.8

CONTROL COMMANDS.......................................................................................................................................52

9.0

SERIAL PORT (UART) .....................................................................................................................................58

9.1

REGISTER DESCRIPTION....................................................................................................................................58

9.2

PROGRAMMABLE BAUD RATE GENERATOR (AND DIVISOR LATCHES DLH, DLL)....................................................64

9.3

EFFECT OF THE RESET ON REGISTER FILE .........................................................................................................64

9.4

FIFO INTERRUPT MODE OPERATION ..................................................................................................................65

9.5

FIFO POLLED MODE OPERTION.........................................................................................................................65

9.6

NOTES ON SERIAL PORT OPERATION .................................................................................................................68

10.0

INFRARED INTERFACE...............................................................................................................................70

10.1

IRDA SIR/FIR AND ASKIR............................................................................................................................70

10.2

CONSUMER IR ..............................................................................................................................................70

10.3

HARDWARE INTERFACE..................................................................................................................................70

10.4

IR HALF DUPLEX TURNAROUND DELAY TIME ...................................................................................................71

10.5

IR TRANSMIT PINS ........................................................................................................................................72

11.0

PARALLEL PORT.........................................................................................................................................73

11.1

IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES..........................................................................74

11.2

EPP 1.9 OPERATION ....................................................................................................................................76

11.3

EPP 1.7 OPERATION ....................................................................................................................................77

11.4

EXTENDED CAPABILITIES PARALLEL PORT .......................................................................................................79

11.5

VOCABULARY................................................................................................................................................79

LPC47N267 Datasheet(PDF) 4 Page - SMSC Corporation

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