LPC47N267 datasheet(88/180 Pages) SMSC

88 / 180 page

SMSC DS – LPC47N267

Page 88

Rev. 10/23/2000

Programmed I/O - Transfers from the Host to the FIFO

In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in

the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty bit needs to be re-read.

Otherwise it may be filled with writeIntrThreshold bytes.

writeIntrThreshold =

(16-<threshold>) free bytes in FIFO

An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to <threshold>.

(If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the FIFO.) The host must

respond to the request by writing data to the FIFO. If at this time the FIFO is empty, it can be completely filled in a single

burst, otherwise a minimum of (16-<threshold>) bytes may be written to the FIFO in a single burst. This process is

repeated until the last byte is transferred into the FIFO.

11.7 Parallel Port Floppy Disk Controller

The Floppy Disk Control signals are available optionally on the parallel port pins. When this mode is selected, the

parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes can be selected

in the Parallel and Serial Extended Setup Register (CR04). PPFD1 has only drive 1 on the parallel port pins; PPFD2

has drive 0 and 1 on the parallel port pins. See the Configuration section for description of the register. The

FDC_PP pin can be used to switch the parallel port pins between the FDC and the parallel port functions. See the

following sub-section.

The following parallel port pins are read as follows by a read of the parallel port register:

Data Register (read) = last Data Register (write)

Control Register read as "cable not connected" STROBE, AUTOFD and SLC = 0 and nINIT =1

Status Register reads: nBUSY = 0, PE = 0, SLCT = 0, nACK = 1, nERR = 1

The following FDC pins are all in the high impedence state when the PPFDC is actually selected by the drive select

nWDATA, DENSEL, nHDSEL, nWGATE, nDIR, nSTEP, nDS1, nDS0, nMTR0, nMTR1.

If PPFDx is selected, then the parallel port can not be used as a parallel port until "Normal" mode is selected.

The FDC signals are muxed onto the Parallel Port pins as shown in Table 43.

For ACPI compliance the FDD pins that are multiplexed onto the Parallel Port function independently of the state of

the Parallel Port controller. For example, if the FDC is enabled onto the Parallel Port the multiplexed FDD interface

functions normally regardless of the Parallel Port Power control, CR01.2.

Table 42 illustrates this functionality.

Table 42 - Modified Parallel Port FDD Control

PARALLEL PORT

POWER

PARALLEL PORT FDC

CONTROL

PARALLEL PORT

FDC STATE

PARALLEL PORT

STATE

CR01.2

CR04.3

CR04.2

OFF

(NOTE

Note

1: The Parallel Port Control register reads as “Cable Not Connected” when the Parallel Port FDC is enabled;

i.e., STROBE = AUTOFD = SLC = 0 and nINIT = 1.

Table 43 – FDC Parallel Port Pins

CONNECTOR

PIN #

QFP

CHIP PIN #

SPP MODE

DIRECTION

FDC MODE

DIRECTION

nSTROBE

I/O

(nDS0)

I/(O) Note1

PD0

I/O

nINDEX

PD1

I/O

nTRK0

PD2

I/O

nWP

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