MT9072AB datasheet(214/275 Pages) ZARLINK

214 / 275 page

MT9072

Data Sheet

214

Zarlink Semiconductor Inc.

17.2.13

Master Control Registers (YF0 - YF6) Bit Functions

Tables 194 to 197 describe the bit functions of each of the Master Control Registers in the MT9072 in E1 Mode(YF0

to YF6). Each register is repeated for each of the 8 framers. Framer 0 is addressed with Y=0, Framer 1 with Y=1,

Framer 2 with Y=2 and so on up to Framer 7 with Y=7 (where Y represents the 4 most significant address bits

(MSB) A11-A8). In addition, a simultaneous write to all 8 framers is possible by setting the MSB address to Y=8

(1000).

A (0), (1) or (#) in the “Name” column of these tables indicates the state of the data bits after a reset (RESET, RSTC

or RST). The (#) indicates that a (0) or (1) is possible.

Bit

Name

Functional Description

15-11

not used.

ADREC

(0)

Address Recognition. When high, this bit will enable address recognition. This forces

the receiver to recognize only those packets having the unique address as programmed

in the Receive Address Recognition Registers or if the address is an All Call Address.

RXEN

(0)

Receive Enable. When low this bit will disable the HDLC receiver. The receiver will

disable after the rest of the packet presently being received is finished. The receiver’s

internal clock is disabled.

When high the receiver will be immediately enabled (depending on the state of RXCEN

input) and will begin searching for flags, Go-aheads etc.

TXEN

(0)

Transmit Enable. When low this bit will disable the HDLC transmitter. The transmitter

will disable after the completion of the packet presently being transmitted. The

transmitter’s internal clock is disabled.

When high the transmitter will be immediately enabled (depending on the state of the

TXCEN input) and will begin transmitting data, or go to a mark idle or interframe time fill

state.

7EOP

(0)

End of Packet When set this bit will indicate an end of packet byte to the transmitter,

which will transmit an FCS following this byte. This facilitates loading of multiple packets

into TX FIFO. Reset automatically after a write to the TX FIFO occurs.

6FA

(0)

Framer Abort.Forms a tag on the next byte written to the TX FIFO, and when set will

indicate to the transmitter that it should abort the packet in which that byte is being

transmitted. Reset automatically after a write to the TX FIFO.

5MI

(0)

Mark-Idle.When low, the transmitter will be in an idle state. When high it is in an

interframe time fill state. These two states will only occur when the TX FIFO is empty.

4CYCLE

(0)

Cycle.When high, this bit will cause the transmit byte count to cycle through the value

loaded into the Transmit Byte Count Register.

TCRCI

(0)

Transmit CRC Inhibit. When high, this bit will inhibit transmission of the CRC. That is,

the transmitter will not insert the computed CRC onto the bit stream after seeing the EOP

tag byte. This is used in V.120 terminal adaptation for synchronous protocol sensitive UI

frames.

SEVEN

(0)

Seven. When high, this bit will enable seven bits of address recognition in the first

address byte. The received address byte must have bit 0 equal to 1 which indicates a

single address byte is being received.

Table 190 - HDLC Control1(YF2) (E1)

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