MT9072AB datasheet(216/275 Pages) ZARLINK

216 / 275 page

MT9072

Data Sheet

216

Zarlink Semiconductor Inc.

17.2.14

Global Control and Status Registers(900-91F) Bit Functions

The Global Control and Status Registers are common to the T1 and E1 operation. The global registers are

accessed by address hex 9xx ( A11 and A8 being high and A10 and A9 being low)

Bit

Name

Functional Description

15-8

not used.

7 - 0

BIT7-0

(00000000)

This eight bit word is tagged with the two status bits from control register 1 (EOP and

FA), and the resulting 10 bit word is written to the TX FIFO. The FIFO status is not

changed immediately after a write or read occurs. It is updated after the data has

settled and the transfer to the last available position has finished. Note that when the

HDLC is connected to a T1 channel, the least significant bit in the FIFO is sent first.

Table 192 - TX Fifo Write Register(YF5) (E1)

Bit

Name

Functional Description

15-8

not used.

7 - 0

CNT7-0

(00000000)

The Transmit Byte Count Register indicating the length of the data portion of the packet

about to be transmitted. This is the size of the data and not the address, flags or FCS.

The Transmit Byte Counter position Y1C determines the number of bytes that have

been sent from the Transmit FIFO.

Table 193 - TX Byte Count Register(YF6) (E1)

Bit

Name

Functional Description

T1E0

(1)

T1E0. This bit determines if the chip will operate in T1 or E1 mode for all 8 framers. If the value

of this bit is changed the chip is reset in E1 or T1 default register mode. If the bit is set to 1, all

the framer register values are set to T1 defaults. For a setting of 0 the register values are set to

E1 defaults. This action takes approximately 34 1.5444 clock cycles. Hence any writes to

registers should be done on the next 125 usec frame after setting or clearing this bit.

STBUS

(0)

ST-BUS Enable. If zero, ST-BUS timing is enabled. If one, GCI timing is enabled (only available

for 2.048 Mb/s mode). See Figures 24-31.

13-5

not used

4CK1

Clock Rate. These clock select bits determine the system clock at the CKi pin and the receive

frame pulse at the FPi pin as follows (See Figures 24 to 31):

CK1

Clock

Frame Pulse

System Bus

4.096 MHz

2.048 Mb/s

16.384 MHz

8.192 Mb/s

3-1

not used.

0RSTC

(0)

Common Reset. When this bit is changed from zero to one, all eight framers will reset to their

default T1 mode. This software reset has the same effect as the RESET pin. See the Reset

Operation section for the default settings.

Table 194 - Global Control0 Register (R/W Address 900) (E1)

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