MT9072AB datasheet(254/275 Pages) ZARLINK

254 / 275 page

MT9072

Data Sheet

254

Zarlink Semiconductor Inc.

Figure 47 - Transmit Data Link Pin Timing

Figure 48 - Receive Data Link Functional Diagram

AC Electrical Characteristics - Transmit Data Link Timing

Characteristics

Sym.

Min.

Typ.

Max.

Units

Test Conditions

Clock Delay

tCD

100

150 pF load on RxDLC

Enable Delay

tED

100

150 pF load on RxDLC

Data Delay Read

tDDR

100

150 pF load on RxDL

Data Hold Read

tDHR

150 pF load on RxDL

MT9072

Inputs Data

tDH

tDS

1.5 Mb/s

Bit Cells

TXCL

1.5 Mhz Clock

TxDL

(Input)

Note 1 - TxDLC output applies for every second frame (FPi) pulse (250 us) only

Note 2 - Clock output provided by setting control bit DLCK=1 (register address Y06)

Note 3 - Enable output provided by clearing control bit DLCK=0 (register address Y06)

Note 4- TXCL is an input 1.5 Mhz clock for the PCM24 interface

Note 5- The TXDLC clock is provided one frame before it is used in ESF Mode in Frames 2 4

TxDLC - Note 3

(Output)

TxDLC - Note 2

(Output)

tCD

tED

tCD

RXBF

RxDLC

RxDL

MT9072AB Datasheet(PDF) 254 Page - Zarlink Semiconductor Inc

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