LM1893 datasheet(13/24 Pages) NSC

13 / 24 page

Component Selection (Continued)

TLH6750 – 22

FIGURE 20 Size CM assuming a 2 bit-time

receive bias time

The impulse noise filter integrator capacitor CI is used to

disallow the passage of any pulse shorter than the integra-

tor charge time That charge time set to a nominal

bit

time is the time required for a g50 mA charge current to

swing CI overa2VBE range Charge time under worst case

conditions must never be greater than a bit time since no

signal could then pass Using a g10% capacitor full junc-

tion temperature range and full specified current range a

maximum nominal charge time of

bit is recommended

Figure 21 gives CI versus data rate under those conditions

The collector pull-up resistor is sized to supply adequate

pull-up current drive and speed while preserving adequate

output low current drive

TLH6750 – 24

FIGURE 21 Impulse noise filter cap CI versus FDATA

where the charge time is

bit time

The 51V silicon zener diode ZA is required when a short

RX-to-TX switch-over time is needed at the same time that

the chip is operating in the RX mode with a pin 10 input

signal swing approaching or exceeding twice the supply

voltage Predominant causes of these large swings imping-

ing on the RX input are 1) a transmitter’s supply voltage

higher than the receiver’s supply voltage 2) a TX and RX

pair that are electrically close or 3) a higher RX T1 step-up

turns ratio than the TX T1 step-down ratio

Normally when in the RX mode with small incoming signal

on pin 10

the ALC remains off with pin 7 at a 6V

(VZb2VBE) bias voltage CA is then charged to 6V TX

mode may then be selected with 6V on CA allowing 100%

TX power to pump T1’s tuned circuit and so the AC line

quickly for fast RX-to-TX switch time As TX output swing

increases so that pin 10 swings below VALC (47V typically)

that ALC activates to charge CA to about 66V to reduce TX

output drive However if in the RX mode pin 10 ever swings

below VALC CA will charge to above 66V Now when the

TX mode is selected with CA at 66V somewhere from 0 to

100% TX output drive is available to pump T1’s tuned circuit

resulting in a slower rising line signal - effectively reducing

the RX-to-TX switch time

Use a 51V ZA driven bya0to 08V logic low signal to

guarantee over-temp operation RA must be in series with

ZA to limit current flow and should never fall below 1 kX If

RA is less than 1 kX then puta2kX resistor in series with

ZA Logic high voltages above 10V will cause current flow

into pin 7 that must be limited to 1 mA (with RA or a

series R)

Breadboarding Tips

During CCT system evaluation some techniques listed be-

low will simplify certain measurements

Use caution when working on this circuit - dangerous

line voltages may be present

When evaluating PLL operation offset cancel circuit op-

eration and loop filter values use the filter of

Figure 22

to view the demodulated signal minus the 2FO and noise

components This filter models the RC lowpass filter on

chip

TLH6750 – 25

FIGURE 22 Circuit to view the differential demodulated data signal minus the noise and 2FO components

conveniently with a single-ended gain-of-one output

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