MCP3919 datasheet(22/88 Pages) MICROCHIP

22 / 88 page

MCP3919

DS20005347A-page 22

 2014 Microchip Technology Inc.

3.11

Serial Data Clock/Master Clock

Input (SCK/MCLK)

This is the serial clock pin for SPI communication. Data

is clocked into the device on the rising edge of SCK.

Data is clocked out of the device on the falling edge of

SCK.

The MCP3919 SPI interface is compatible with SPI 0,0

and 1,1 modes. SPI modes can be changed during a

CS high time.

The maximum clock speed specified is 20 MHz. SCK

and MCLK are two different and asynchronous clocks;

SCK is only required when a communication happens,

while MCLK is continuously required when the part is

converting analog inputs.

This input is Schmitt-triggered.

In the 2-Wire Interface mode, this pin defines the mas-

ter clock of the device (MCLK) and simultaneously the

serial clock (SCK) for the interface. In this mode, the

clock has to be provided continuously to ensure proper

operation. See Section 7.0 “2-Wire Serial Interface

Description”

for more information and timing dia-

grams of the 2-wire interface protocol.

3.12

Serial Data Output (SDO)

This is the SPI data output pin. Data is clocked out of

the device on the falling edge of SCK.

This pin remains in a high-impedance state during the

command byte. It also stays high-impedance during the

entire communication for write commands and when

the CS pin is logic high, or when the RESET pin is logic

low. This pin is active only when a read command is

processed. The interface is half-duplex (inputs and

outputs do not happen at the same time).

3.13

Serial Data/OSR1 Logic Input

(SDI/OSR1)

This is the SPI data input pin. Data is clocked into the

device on the rising edge of SCK. When CS is logic low,

this pin is used to communicate with a series of 8-bit

commands. The interface is half-duplex (inputs and

outputs do not happen at the same time).

Each communication starts with a chip select falling

edge followed by an 8-bit command word, entered

through the SDI pin. Each command is either a Read or

a Write command. Toggling SDI after a Read or Write

command or when CS is logic high has no effect.

This input is Schmitt-triggered.

In 2-Wire Interface mode, this is the OSR1 logic select

input pin (see Section 7.0 “2-Wire Serial Interface

Description”

for the logic input table for OSR0 and

OSR1). The pin state is latched when the MODE

changes to 2-Wire Interface mode, and is relatched at

each watchdog timer reset.

3.14

Master Reset/OSR0 Logic Input

(RESET/OSR0)

In SPI mode, this pin is active low and places the entire

chip in a Reset state when active.

When RESET is logic low, all registers are reset to their

default value, no communication can take place and no

clock is distributed inside the part, except in the input

structure if MCLK is applied (if MCLK is idle, then no

clock is distributed). This state is equivalent to a Power-

On Reset (POR) state.

Since the default state of the ADCs is on, the analog

power consumption when RESET is logic low is

equivalent to when RESET is logic high. Only the digital

power consumption is largely reduced because this

current consumption is essentially dynamic and is

reduced drastically when there is no clock running.

All the analog biases are enabled during a Reset, so

that the part is fully operational just after a RESET

rising edge, if MCLK is applied when RESET is logic

low. If MCLK is not applied, there is a time after a hard

reset when the conversion may not accurately

correspond to the startup of the input structure.

This input is Schmitt-triggered.

In 2-Wire Interface mode, this is the OSR0 logic select

pin (see Section 7.0 “2-Wire Serial Interface

Description”

for the logic input table for OSR0 and

OSR1). The pin state is latched when the mode

changes to 2-Wire Interface mode, and is relatched at

each watchdog timer reset.

3.15

Digital Power Supply (DVDD)

DVDD is the power supply voltage for the digital circuitry

within the MCP3919. It is distributed on several pins

(pins 12 and 24 in the QFN package, one pin only in the

SSOP-28 package). For optimal performance, it is

recommended to connect these pins together using a

star connection and to connect appropriate bypass

capacitors (typically a 10 µF in parallel with a 0.1 µF

ceramic). DVDD should be maintained between 2.7V

and 3.6V for specified operation.

At least one of these pins need to be properly con-

nected to ensure proper functionality of the device. All

of these pins need to be properly connected to ensure

optimal performance of the device. If any of these pins

are left floating, the accuracy and noise specifications

are not ensured.

3.16

Exposed Thermal Pad

This pin must be connected to AGND or left floating for

proper operation. Connecting it to AGND is preferable

for lowest noise performance and best thermal

behavior.

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