PC87310 datasheet(38/52 Pages) NSC

38 / 52 page

40 Functional Description (Continued)

through use of the PC87310 is the IDE (Intelligent Drive

lectronics) Hard Disk interface The SuperIO provides the

two hard disk chip selects required for this interface Using

the SuperIO only five other chips are required to construct

the IDE Hard Disk Interface circuit (see

Figure 7 ) The circuit

shown provides the address decoding buffers and control

and data signals for the hard disk IDE interface

The IDE interface is essentially the AT bus ported to the

hard drive The hard disk controller resides on the hard drive

itself So the IDE interface circuit must provide the AT bus

signals including data bits D15 – D0 address lines A3 – A0

as well as the common control signals These signals are

contained on the 40-pin IDE interface header (see

Figure 7 )

When in the PC-AT mode The PC87310 SuperIO control-

ler provides the two hard disk chip selects for the IDE inter-

face The HCS0 output is active low when the 1F0 – 1F7

(hex) IO address space is chosen and corresponds to the

1FX signal on the IDE header The HCS1 output is active

low when the 3F6 or 3F7 IO addresses are chosen and

corresponds to 3FX on the IDE header These are the two

address blocks used in the PC-AT hard disk controller The

table below summarizes the addresses used by the PC-AT

hard disk controller

Looking at the IDE interface circuit in more detail the LS244

provides buffering of the control and address lines The

16L8 PAL provides the necessary control signals to enable

the data lines for the correct addresses These four control

signals ENHI ENLO D7RD and D7WR are active low

based on the PAL equations (see

Figure 6 )

To summarize the function of these PAL control signals

ENHI enables the LS245 octal bus transceiver for the upper

data lines (D15 – D8) for 16-bit read and write operations at

addresses 1F0 – 1F7 ENHI will activate the LS245 only if

the IOCS16 output from the hard drive is active ENLO en-

ables the other LS245 octal bus transceiver for the lower

data lines (D7 – D0) for 1F0 – 1F7 reads and writes and for

3F6 writes and 3F7 reads In addition the D7RD and D7WR

control lines from the PAL insure that the D7 data line is

disabled for address 3F7 (this bit is used for the Disk

Changed register on the floppy disk controller) The two

LS245 chips are used to enable or TRI-STATE these data

signals The LS125 is used to buffer or TRI-STATE the D7

data line and the HCS0 chip select

PC-AT Hard Disk Controller Registers

Address

Read Function

Write Function

1F0

Data Register

1F1

Error Register

Write Precomp Register

1F2

Sector Count

1F3

Sector Number

1F4

Cylinder Low

1F5

Cylinder High

1F6

SDH Register

1F7

Status Register

Command Register

3F6

Not Used Data Bus TRI-STATE

Digital Output Register

3F7

Drive Address Register (Note)

Not Used Data Bus TRI-STATE

Note

Data bit D7 is used by the Floppy Disk Controller at address 3F7 D7 must be TRI-STATED by the IDE interface circuit at this address

module SIOpal

flag

-r2

title

Address decode PAL for SuperIO demo board

PC87310EB 20

Steve Horeff

PC Peripherals 1289

SI05 device ’P16L8

VCC

GND

PIN 20

RESET

XTSEL

HCS0

HCS1

PIN 1

IOR

IOW

1016CS

PIN 5

D7WR

D7RD

PIN 18

ENLO

ENHI

PIN 12

RESET

PIN 11

equations

RESET

4 (RESET)

D7RD

4 (EN * ( IOR*

HCS0))

D7WR

4 (EN * ( IOW *(( HCS1 * A0) 0

HCS0)))

ENHI

4 (EN * (( 1O16CS *

HCS0) * (

IOR

IOW)))

ENLO

4 (EN * (( HCS0 * ( IOR 0

IOW))

(

HCS1 * ((A0 *

IOR)

0 (A0 *

IOW)))))

end SIO

pal

FIGURE 6 PAL (16R4) Pin Definitions Equations

PC87310 Datasheet(PDF) 38 Page - National Semiconductor (TI)

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