PC87310 datasheet(8/52 Pages) NSC

8 / 52 page

20 Pin Descriptions (Continued)

Pin Symbol

Pin Number

Description

DCD1 2

(Data Carrier Detect)

52 47

When low this input indicates that the data carrier has been detected by

the MODEM or data set The DCD signal is a MODEM status input

whose condition the CPU can test by reading bit 7 (DCD) of the MODEM

Status Register Bit 7 is the complement of the DCD signal Bit 3 (DDCD)

of the MODEM Status Register indicates whether the DCD input has

changed state since the previous reading of the MODEM Status

Note

Whenever the DCD bit of the MODEM Status Register changes state an interrupt is

generated if the MODEM Status Interrupt is enabled

DIR

(Direction)

This output determines the direction of the head movement (low e step

in high e step out) When in the write or read modes this output will be

high This is a high drive open drain output

DR0 1

(Drive)

93 92

These are active low drive select outputs for drive 0 and drive 1 They

are ANDed with the corresponding motor enable lines This is a high

drive open drain output These pins contain encoded drive select

information if bit 7 of the Configuration Register is set (see Configuration

DRQ

(DMA Request)

Active high output to signal the DMA controller that a data transfer is

needed This signal is enabled when D3 of the Drive Control Register is

set However the specify command must be used to enable the DMA

mode

DRVTYP

(Drive Type)

This is an input used by the controller to enable the 300 kbs mode This

enables the use of floppy drives with either dual or single speed spindle

motors For dual speed spindle motors this pin is tied low When low

and 300 kbs data rate is selected in the data rate register the PLL

actually uses 250 kbs This pin is tied high for single speed spindle

motor drives (standard AT drive) When this pin is high and 300 kbs is

selected 300 kbs is used (See also RPMLC pin)

DSKCHGRG

This disk interface input indicates when the disk drive door has been

(Disk ChangeRead Gate)

opened The active high state of this input is read from bit D7 of address

3F7 hex When the RG bit in the Mode Command is set this pin

functions as a Read Gate signal When low it forces the data separator

to lock to the crystal and when high it locks to the data for diagnostic

purposes

DSR1 2

(Data Set Ready)

53 46

When low this input indicates that the MODEM or data set is ready to

establish the communications link with the UART The DSR signal is a

MODEM status input whose condition the CPU can test by reading bit 5

(DSR) of the MODEM Status Register Bit 5 is the complement of the

DSR signal Bit 1 (DDSR) of the MODEM Status Register indicates

whether the DSR input has changed state since the previous reading of

the MODEM Status Register

Note

Whenever the DSR bit of the MODEM Status Register changes state an interrupt is

generated if the MODEM Status Interrupt is enabled

DTR1 2

(Data Terminal Ready)

54 44

When low this output indicates to the MODEM or data set that the

UART is ready to establish a communications link The DTR output

signal can be set to an active low by programming bit 0 (DTR) of the

MODEM Control Register to a high level A Master Reset operation sets

this signal to its inactive (high) state Loop mode operation holds this

signal in its inactive state if the XTSEL pin is high during reset If the

XTSEL pin is low during reset the associated pin state is controlled by

the MCR0 bit during loop mode operation These are dual function pins

see CRB2 and CRB3 for detailed operation during reset

ERR

(Error)

This input is set low by the printer when it has detected an error

FILTER

This pin is the output of the charge pump and the input to the VCO One

or more filters are attached between this pin and the VSSA FGND250

and FGND500 pins

FGND250

This pin connects the PLL filter for 250k(MFM)125k(FM) bs or

(Filter Ground 250 kbs)

300k(MFM)150k(FM) bs to ground This is a low impedance open

drain output

FGND500

This pin connects the PLL filter for 500k(MFM)250k(FM) bs to ground

(Filter Ground 500 kbs)

This is a low impedance open drain output

PC87310 Datasheet(PDF) 8 Page - National Semiconductor (TI)

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