PC87310 datasheet(14/52 Pages) NSC

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40 Functional Description (Continued)

TABLE 4-2 Encoded Drive and Motor Pin Information

(Configuration Register Bit 7 e 1)

Drive Control Register Bits

Drive Control Pins

Decoded Function

543210DR1

DR0

MTR1

MTR0

Activate Drive 0 and Motor 0

Activate Drive 1 and Motor 1

Activate Drive 2 and Motor 2

Activate Drive 3 and Motor 3

The pin states shown in Table 4-2 are the direct results of

the bit patterns shown All other bit patterns produce pin

states that should NOT be decoded to enable any drive or

motor In other words all other bit patterns except the four

shown in Table 4-2 are invalid and should disable all drives

and motors when Configuration Register bit 7 e 1

43 SERIAL PORTS

431 Introduction

Each of these serial ports function as a data inputoutput

interface in a microcomputer system The system software

determines the functional configuration of the UARTs via a

TRI-STATE 8-bit bidirectional data bus

The UARTs are completely independent They perform seri-

al-to-parallel conversion on data characters received from a

peripheral device or a MODEM and parallel-to-serial con-

version on data characters received from the CPU The

CPU can read the complete status of either UART at any

time during the functional operation Status information re-

ported includes the type and condition of the transfer opera-

tions being performed by the UART as well as any error

conditions (parity overrun framing or break interrupt)

The UARTs have programmable baud rate generators that

are capable of dividing the timing reference clock input by

divisors of 1 to (216b1) and producing a 16 c clock for

driving the internal transmitter logic Provisions are also in-

cluded to use this 16 c clock to drive the receiver logic The

UARTs have complete MODEM-control capability and a

processor-interrupt system Interrupts can be programmed

to the user’s requirements minimizing the computing re-

quired to handle the communications link

The UARTs can operate in the INS8250-B mode (XT) or the

NS16450 mode (AT) depending on the state of the XTSEL

pin during reset

432 Serial Port Registers

TABLE 4-3 Register Addresses (IOL e 0 AEN e 0)

DLAB1

CHSL

Receiver Buffer (Read)

Transmitter Holding (Write)

Interrupt Enable

Interrupt Identification (Read)

Test Control (Write)

Line Control

MODEM Control

Line Status

MODEM Status

Scratch (Note 1)

Divisor Latch

(Least Significant Byte)

Divisor Latch

(Most Significant Byte)

DLAB2

CHSL

Receiver Buffer (Read)

Transmitter Holding (Write)

Interrupt Enable

Interrupt Identification (Read)

Test Control (Write)

Line Control

MODEM Control

Line Status

MODEM Status

Scratch (Note 1)

Divisor Latch

(Least Significant Byte)

Divisor Latch

(Most Significant Byte)

Note 1

This register is only present when operating in the AT NS16450 mode (XTSEL is high during reset)

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