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CAM35C44 Datasheet(PDF) 26 Page - SMSC Corporation

Part # CAM35C44
Description  Infrared Communications Controller Chip CameraFR
PDF  50 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

CAM35C44 Datasheet(HTML) 26 Page - SMSC Corporation

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TABLE 20 - SOFTWARE SELECT A REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
CR05
R/W
Software Select A
0x00
CR06 - Software Select B
The Software Select B register CR06 is directly
connected to the read-only IrCC 2.0 Software
Select B register in SCE Register Block Three.
Writing
to
CR06
is
the
only
way
to revise the contents of the Software Select B
register.
CR06 can only be accessed in the
configuration state and only after the CSR has
been initialized to 06H. The default value of this
register after power up is 00H (TABLE 21).
TABLE 21 - SOFTWARE SELECT B REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
DEFAUL
T
CR06
R/W
Software Select B
0x00
CR07 - IR Half Duplex Time-Out
CR07 is the IR Half Duplex Time-Out register
(TABLE 22).
If the Half Duplex option is selected (see section
HALF DUPLEX, Bit 2 on page 24), the IR half
duplex
time-out
constrains
the
timing
of
transmit/receive direction mode changes in the
IrCC 2.0. The IR half duplex time-out is started
as each IR message data bit is transferred and
prevents direction mode changes until the time-
out expires.
The timer is restarted whenever
new data is transferred in the current direction
mode.
For example, in an SIR mode if data is loaded
into the transmit buffer while a character is being
received,
the
transmission
will
not
start
until the last bit has been received and the time-
out expires. If the start bit of another character
is received during this time-out, the timer is
restarted after the new character is received.
The IRCC block in the CAM35C44 also includes
an 8 bit IR half duplex time-out register, like
CR07, in SCE Register Block 5. These two
registers behave like the other IRCC legacy
controls where either source uniformly updates
the value of both registers when either register is
explicitly written using IOW or following a device-
level POR. IRCC software resets do not affect
these registers.
The IR half duplex time-out is programmable
from 0 to 25.5ms in 100
#s increments, as
follows:
IR HALF DUPLEX TIME-OUT = (CR07) x 100
####s
TABLE 22 - IR HALF DUPLEX TIME-OUT REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
CR07
R/W
IR HALF DUPLEX TIME-OUT
0x03



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