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M68SDIL Datasheet(PDF) 30 Page - Motorola, Inc |
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M68SDIL Datasheet(HTML) 30 Page - Motorola, Inc |
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30 / 460 page  General Description Technical Data MC68HC912D60A — Rev 3.0 30 General Description MOTOROLA Figure 1-2 . MC68HC912D60A 80-pin QFP Block Diagram PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 TxCAN KWG4 KWG3 KWG2 KWG1 KWG0 PG7 KWG6 KWG5 PG4 PH4 KWH4 KWH3 KWH2 KWH1 KWH0 KWH7 KWH6 KWH5 PGUPD(VDD) PHUPD(VSS) IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 60K byte flash EEPROM 2K byte RAM Enhanced SPI PE1 PE2 PE4 PE5 PE6 PE3 VDDAD VSSAD RESET EXTAL XTAL PW0 PW1 PW2 PW3 PWM PP0 PP1 PP2 PP3 VDD ×2 VSS ×2 SCI0 (MI BUS) RxD0 TxD0 RxD1 TxD1 SISO/MISO MOMI/MOSI SCK SS PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 1K byte EEPROM PE0 PE7 BKGD capture timer SCI1 CPU12 Periodic interrupt COP watchdog Clock monitor Single-wire background debug module Breakpoints PLL VSSPLL XFC VDDPLL CAN RxCAN DDRA PORT A DDRB PORT B Multiplexed Address/Data Bus PAD03 PAD04 PAD05 PAD06 PAD07 VRH0 VRL0 PAD00 PAD01 PAD02 AN03 AN04 AN05 AN06 AN07 VDDAD VSSAD VRH0 VRL0 AN00 AN01 AN02 ATD0 I/O Wide bus Narrow bus PCAN1 PCAN0 VDDX ×2 VSSX ×2 Power for internal circuitry Power for I/O drivers PP4 PP5 PP6 PP7 PCAN7 PCAN6 PCAN5 PCAN4 PCAN3 PCAN2 ECLK R/W LSTRB/TAGLO MODA/IPIPE0 MODB/IPIPE1/CGMTST XIRQ DBE/CAL/ECLK Lite IRQ integration module (LIM) AN13 AN14 AN15 AN16 AN17 VDDAD VSSAD VRH1 VRL1 AN10 AN11 AN12 ATD1 Several I/O on ports G, H and CAN are unavailable externally on the 80-pin QFP package. These in- ternal pins should either be defined as outputs or have their pull-ups/downs enabled. Note: Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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