TH71221 datasheet(15/44 Pages) MELEXIS

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TH71221

27 to 930MHz

FSK/FM/ASK Transceiver

39010 071221

Page 15 of 44

Data Sheet

Rev. 009

Nov/15

VEE

VCC

3pF

OUT_PA

VCC

3.2.5 FSK Demodulator

The implemented FSK demodulator is based on the phase-coincidence principle. A discriminator tank, which

can either consist of a ceramic discriminator or an LC tank, is connected to pin IN_DEM. If FSK mode is

selected SW1 is open, SW2 is closed and the output of OA2 is multiplexed to pin INT2/PDO.

The demodulator output signal directly feeds the data slicer setup by means of OA1. The data slicer time

constant can be calculated using (8). This time constant should be larger than the longest possible bit dura-

tion of the data stream as described in the previous paragraph.

An on-chip AFC circuit tolerates input frequency variations. The input frequency acceptance range is propor-

tional to the FSK or FM deviation. It can be adjusted by the discriminator tank. The AFC feature is disabled

by default and can be activated in programmable mode.

3.3

Transmitter Part

The output of the PLL frequency synthesizer feeds a power amplifier (PA) in order to setup a complete RF

transmitter. The VCO frequency is identical to the carrier frequency.

3.3.1 Power Amplifier

The power amplifier (PA) has been designed to deliver about 10 dBm in the specified frequency bands. Its

pin OUT_PA is an open collector output. The larger the output voltage swing can be made the better the

power efficiency will be. The PA must be matched to deliver the best efficiency in terms of output power and

current consumption.

The collector must be biased to the positive supply. This is

done by means of an inductor parallel tuned with a capaci-

tor. Or it is made large enough in order not to affect the out-

put matching network. S-parameters of pin OUT_PA are not

useful because the output is very high resistive with a small

portion of parallel capacitance. Since the open-collector

output transistor can be considered as a current source, the

only parameters needed to design the output matching net-

work are the output capacitance, the supply voltage VCC, the

transistor’s saturation voltage and the power delivered to the

load PO.

In order to avoid saturation of the output stage, a saturation

voltage VCESAT of about 0.7 V should be considered. The

real part of the load impedance can then be calculated using

Fig. 7:

OUT_PA schematic

SAT

)

VCE







(9)

The output capacitance is typically 3 pF.

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