WT6124 datasheet(3/39 Pages) ETC

3 / 39 page

WT6132/WT6124/WT6116

Data Sheet Rev. 1.01

Weltrend Semiconductor, Inc.

Page 4

FUNCTIONAL DESCRIPTION

CPU

8-bit 6502 compatible CPU operates at 6MHz. Address bus is 16-bit and data bus is 8-bit.

The non-maskable interrupt (/NMI) of 6502 is modified to be maskable and is defined as INT0 with higher

priority. The interrupt request (/IRQ) of 6502 is defined as INT1 with lower priority.

Please refer the 6502 reference menu for more detail.

RAM

WT6132 and WT6124 have 512 bytes RAM. Address is located from $0080h to $00FFh and $0180h to

$02FFh.

WT6116 have 384 bytes RAM. Address is located from $0080h to $00FFh and $0180h to $027Fh.

ROM

For WT6132, ROM is located from $8000h to $FFFFh.

For WT6124, ROM is located from $A000h to $FFFFh.

For WT6116, ROM is located from $C000h to $FFFFh.

The following addresses are reserved for special purpose :

$FFFAh (low byte) and $FFFBh (high byte) : INT0 interrupt vector.

$FFFCh (low byte) and $FFFDh (high byte) : program reset interrupt vector.

$FFFEh (low byte) and $FFFFh (high byte) : INT1 interrupt vector.

$0000h

$003Fh

Registers

$0040h

$007Fh

Reserved

$0080h

$00FFh

128 bytes RAM

$0100h

$017Fh

Reserved

$0180h

$02FFh

384 bytes RAM

$0300h

$0FFFh

Reserved

$1000h

$7FFFh

Reserved

$8000h

$FFFFh

ROM

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