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AD4000

Data Sheet

Rev. 0 | Page 20 of 32

RC FILTER BANDWIDTHS (Hz),

RESISTOR (Ω), CAPACITOR (pF)

–115

–105

–110

–100

–95

–90

–85

–80

–70

–75

260.482kHz

1.3kΩ

470pF

497.981kHz

680Ω

470pF

1.3MHz

680Ω

180pF

2.27MHz

390Ω

180pF

4.42MHz

200Ω

180pF

ADA4077-1 HIGH-Z ENABLED

ADA4077-1 HIGH-Z DISABLED

ADA4610-1 HIGH-Z ENABLED

ADA4610-1 HIGH-Z DISABLED

Figure 40. THD vs. RC Bandwidth for Various Precision ADC Drivers, VREF = 5 V,

fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled)

Long Acquisition Phase

The AD4000 also features a very fast conversion time of 290 ns,

which results in a long acquisition phase. The acquisition is further

extended by a key feature of the AD4000: the ADC returns back

to the acquisition phase typically 100 ns before the end of the

conversion. This feature provides an even longer time for the ADC

to acquire the new input voltage. A longer acquisition phase

reduces the settling requirement on the driving amplifier, and a

lower power/bandwidth amplifier can be chosen. The longer

acquisition phase means that a lower RC filter cutoff can be used,

which means a noisier amplifier can also be tolerated. A larger

value of R can be used in the RC filter with a corresponding smaller

value of C, reducing amplifier stability concerns without impacting

distortion performance significantly. A larger value of R also

results in reduced dynamic power dissipation in the amplifier.

See Table 10 for details on setting the RC filter bandwidth and

choosing a suitable amplifier.

VOLTAGE REFERENCE INPUT

A 10 µF (X7R, 0805 size) ceramic chip capacitor is appropriate

for the optimum performance of the reference input.

For higher performance and lower drift, use a reference such as

the ADR4550. Use a low power reference such as the ADR3450

at the expense of a slight decrease in the noise performance. It is

recommended to use a reference buffer such as the ADA4807-1

between the reference and the ADC reference input. It is important

to consider the optimum size of capacitance necessary to keep

the reference buffer stable as well as to meet the minimum ADC

requirement stated previously in this section.

POWER SUPPLY

The AD4000 uses two power supply pins: a core supply (VDD) and

a digital input/output interface supply (VIO). VIO allows direct

interface with any logic between 1.8 V and 5.5 V. To reduce the

number of supplies needed, VIO and VDD can be tied together

for 1.8 V operation. The ADP7118 low noise, CMOS, low

dropout (LDO) linear regulator is recommended to power the

VDD and VIO pins. The AD4000 is independent of power supply

sequencing between VIO and VDD. Additionally, the AD4000 is

insensitive to power supply variations over a wide frequency

range, as shown in Figure 41.

100

10k

100k

FREQUENCY (Hz)

Figure 41. PSRR vs. Frequency, VIO = 3.3 V, VREF = 5 V

The AD4000 powers down automatically at the end of each

conversion phase; therefore, the power scales linearly with the

sampling rate. This feature makes the device ideal for low

sampling rates (even of a few hertz) and low battery-powered

applications. Figure 42 shows the AD4000 total power

dissipation and individual power dissipation for each rail.

100

10k

100k

THROUGHPUT (Hz)

0.01

0.1

100

10k

100k

VDD

VIO

VREF

TOTAL POWER

Figure 42. Power Dissipation vs. Throughput, VIO = 1.8 V, VREF = 5 V

DIGITAL INTERFACE

Although the AD4000 has a reduced number of pins, it offers

flexibility in its serial interface modes. The AD4000 can also be

programmed via 16-bit SPI writes to the configuration registers.

When in CS mode, the AD4000 is compatible with SPI, QSPI™,

digital hosts, and DSPs. In this mode, the AD4000 can use either a

3-wire or 4-wire interface. A 3-wire interface using the CNV,

SCK, and SDO signals minimizes wiring connections, which is

useful, for instance, in isolated applications. A 4-wire interface

using the SDI, CNV, SCK, and SDO signals allows CNV, which

initiates the conversions, to be independent of the readback

timing (SDI). This interface is useful in low jitter sampling or

simultaneous sampling applications.

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