LMX2364SLEX datasheet(22/39 Pages) NSC

22 / 39 page

Input Impedance

20050676

The above block diagram shows the test procedure measur-

ing the input impedance for the LMX2364. This applies to the

FinRF, FinIF, OSCinRF, and OSCinIF pins. The input imped-

ance of the CSP and the TSSOP package should always be

assumed to be different, until proven otherwise. The basic

test procedure is to calibrate the network analyzer, ensure

that the part is powered up, and then measure the input

impedance.

The network analyzer can be calibrated by using either

calibration standards or by soldering resistors directly to the

evaluation board. An open can be implemented by putting no

resistor, a short can be implemented by usinga0ohm

resistor, and a short can be implemented by using two 100

ohm resistors in parallel. Note that no DC blocking capacitor

is used for this test procedure. This is done with the PLL

removed from the PCB. This requires the use of a clamp

down fixture that may not always be generally available. If no

clamp down fixture is available, then this procedure can be

done by calibrating up to the point where the DC blocking

capacitor usually is, and then adding a 0 ohm resistor back

for the actual measurement.

Once that the network analyzer is calibrated, it is necessary

to ensure that the PLL is powered up. This can be done by

toggling the power down bits (RF_PD and IF_PD) and ob-

serving that the current consumption indeed increases when

the bit is disabled. Sometimes it may be necessary to apply

a signal to the OSCinIF pin in order to program the part. If

this is necessary, disconnect the signal once it is established

that the part is powered up.

It is useful to know the input impedance of the PLL for the

purposes of debugging RF problems and designing match-

ing networks. Another use of knowing this parameter is make

the trace width on the PCB such that the input impedance of

this trace matches the real part of the input impedance of the

PLL frequency of operation. In general, it is good practice to

keep trace lengths short and make designs that are relatively

resistant to variations in the input impedance of the PLL.

LMX2364SLEX Datasheet(PDF) 22 Page - National Semiconductor (TI)