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LMX2364SLEX Datasheet(PDF) 34 Page - National Semiconductor (TI) |
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LMX2364SLEX Datasheet(HTML) 34 Page - National Semiconductor (TI) |
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34 / 39 page ![]() Supplemental Information 3.0 USE OF THE DIGITAL LOCK DETECT FUNCTION The Lock Detect Digital Filter compares the difference be- tween the phase of the inputs of the phase detector to a RC generated delay of approximately 15nS. To enter the locked state (Lock = HIGH) the phase error must be less than the 15nS RC delay for 5 consecutive reference cycles. Once in lock (Lock = HIGH), the RC delay is changed to approxi- mately 30nS. To exit the locked state (Lock = LOW), the phase error must become greater than the 30nS RC delay. When the PLL is in the power down mode, Lock is forced LOW. A flow chart of the digital filter is shown below. 20050604 www.national.com 34 |
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