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MAX1167BEEE Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MAX1167BEEE Datasheet(HTML) 5 Page - Maxim Integrated Products |
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5 / 30 page  Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters _______________________________________________________________________________________ 5 ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Shutdown Supply Current IAVDD + IDVDD CS = DVDD, SCLK = 0, DIN = 0, DSPR = DVDD, full power-down 0.6 10 µA Power-Supply Rejection Ratio PSRR AVDD = DVDD = 4.75V to 5.25V, full-scale input (Note 9) 63 dB TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16) (AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Acquisition Time tACQ External clock (Note 6) 729 ns SCLK to DOUT Valid tDO CDOUT = 30pF 50 ns CS Fall to DOUT Enable tDV CDOUT = 30pF 80 ns CS Rise to DOUT Disable tTR CDOUT = 30pF 80 ns CS Pulse Width tCSW 100 ns SCLK rise CS to SCLK Setup tCSS SCLK fall (DSP) 100 ns SCLK rise CS to SCLK Hold tCSH SCLK fall (DSP) 0ns Conversion 93 SCLK High Pulse Width tCH Duty cycle 45% to 55% Data transfer 50 ns Conversion 93 SCLK Low Pulse Width tCL Duty cycle 45% to 55% Data transfer 50 ns SCLK Period tCP 209 ns SCLK rise DIN to SCLK Setup tDS SCLK fall (DSP) 50 ns SCLK rise DIN to SCLK Hold tDH SCLK fall (DSP) 0ns CS Falling to DSPR Rising tDF 100 ns DSPR to SCLK Falling Setup tFSS 100 ns DSPR to SCLK Falling Hold tFSH 0ns |
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