LM4930 datasheet(30/33 Pages) NSC

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Application Information (Continued)

HP Sense Out (J6)

Function

AGND

HPSense_Out

IRQ (J4)

Function

DGND

IRQ

Onboard MCLK Select (S2)

Jumper IN = Onboard MCLK

Jumper OUT = External MCLK

LM4930ITL DEMO BOARD OPERATION

The LM4930ITL demo board is a complete evaluation plat-

form, designed to give easy access to the control pins of the

part and comprise all the necessary external passive com-

ponents. Besides the separate analog (J9) and digital (J10)

supply connectors, the board features seven other major

input and control blocks: a two wire interface bus (J1) for the

control lines, a PCM interface bus (P1-P4) for voiceband

digital audio, an I2S interface bus (J2) for full-range digital

audio, an analog mic jack input (J3) for connection to an

external microphone, a BTL mono output (J7) for connection

to an external speaker, a stereo headphone output (J8), and

an external MCLK input (P5) for use in place of the crystal on

the demoboard.

Two-wire Interface Bus (J1)

This is the main control bus for the LM4930. It is a two-wire

interface with an SDA line (data) and SCL line (clock). Each

transmission from the baseband controller to the LM4930 is

given MSB first and must follow the timing intervals given in

the Electrical Characteristics section of the datasheet to

create the start and stop conditions for a proper transmis-

sion. The start condition is detected if SCL is high on the

falling edge of SDA. The stop condition is detected if SCL is

high on the rising edge of SDA. Repeated start signals are

handled correctly. Data is then transmitted as shown in

Figure 2. After the start condition has been achieved the chip

address is sent, followed by a set write bit, wait for ack (SDA

will be pulled low by LM4930), data bits 15-8, wait for ACK

(SDA will be pulled low by LM4930), data bits 7-0, wait for

ACK (SDA will be pulled low by LM4930)and finally the stop

condition is given.

This same sequence follows for any control bus transmis-

sion to the LM4930. The chip address is hardwire selected

by the ADR Select pin which may be jumpered high or low

with its application at S1 on the demo board. The chip

address is then given as a combination of the identifying bits

for the LM4930 plus the 2-bit address of the desired control

GainConfig). Acceptable addresses are shown here in Table

Table 1. LM4930 Control Bus Addresses

Address Bits

Address

ADR=0

543210

010000

010001

010010

ADR=1

110000

110001

110010

Data is sampled only if the address is in range and the R/W

bit is clear. Data for each register is given in the System

Control Registers section of the datasheet. National Semi-

conductor also features a special control board for quick

evaluation of the LM4930 demo board with your PC. This is

a serial control interface board, complete with header com-

patible with the interface header (J1) on the LM4930 board.

This also features demonstration software to allow for com-

plete control and evaluation of the various modes and func-

tions of the LM4930 through the bus.

Pullup resistors are required to achieve reliable operation.

750

Ω pullup resistors on the SDA and SCL lines achieves

best results when used with National’s parallel-to-serial in-

terface board. Lower value pullup resistors will decrease the

rise and fall times on the bus which will in turn decrease

susceptibility to bus noise that may cause a false trigger. The

cost comes at extra current use. Control bus reliability will

thus depend largely on bus noise and may vary from design

to design. Low noise is critical for reliable operation.

PCM Bus Interface (P1, P2, P3, P4)

PCM_SDO (P4), PCM_SYNC (P3), PCM_SDI (P1), and

PCM_CLK (P2) form the PCM interface bus for simple com-

munication with most baseband ICs with voiceband commu-

nications and follow the PCM-1900 communications stan-

dard. The PCM interface features frame lengths of 16, 32, or

64 bits, A-law and u-law companding, linear mode, short or

long frame sync, an energy-saving power down mode, and

master only operation.

The PCM bus does not support a slave mode. It operates as

a master only. Thus PCM_SYNC and PCM_CLK are solely

generated by the LM4930. PCM_SYNC is the word sync line

LM4930 Datasheet(PDF) 30 Page - National Semiconductor (TI)

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