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LM4930 Datasheet(PDF) 15 Page - National Semiconductor (TI) |
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LM4930 Datasheet(HTML) 15 Page - National Semiconductor (TI) |
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15 / 33 page ![]() Electrical Characteristics DV DD = 3V, AVDD = 3V, RLHP =32Ω,RLHF =8Ω (Notes 1, 2, 3) (Continued) The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for T A= 25˚C. Symbol Parameter Conditions LM4930 Units (Limits) Typical (Note 6) Limits (Notes 7, 15) t SDAS SDA_DATA Setup Time 500 ns f CLKPCM PCM_CLK Frequency PCM_SYNC_MODE = 00 PCM_SYNC_MODE = 01 PCM_SYNC_MODE = 10 128 256 512 kHz kHz kHz PCM_CLK Duty Cycle 50 40 60 % (min) % (max) f CLKI2S I2S_CLK Frequency I2S_RES = 0 I2S_RES = 1 1.536 3.072 MHz MHz I2S_CLK Duty Cycle 50 40 60 % (min) % (max) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 2: All voltages are measured with respect to the relevant GND pin unless otherwise specified. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX =(TJMAX –TA)/ θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4930, see power derating currents for more information. Note 4: Human body model: 100pF discharged through a 1.5k Ω resistor. Note 5: Machine model: 220pF - 240pF discharged through all pins. Note 6: Typicals are measured at 25˚C and represent the parametric norm. Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Best operation is achieved by maintaining 3.0V ≤ AVDD ≤ 5.0 and 3.0V ≤ DVDD ≤ 3.6V. AVDD must be equal to or greater than DVDD. for proper operation. Note 9: The sampling clock frequency is equal to the master clock frequency divided by 256. (fconv =fMCLK/256) Note 10: This value represents the 0dB output level of the given amplifier for the given analog supply voltage. Gain values given in the GAINCONFIG register are relative to these full-scale values for each output amplifier. Note 11: To ensure a successful transistion into Powerdown Mode, ZXD_DISABLE must be set whenever there is no audio input signal present. Note 12: It is recommended to alter this bit only while the part is in Powerdown Mode. Note 13: Reserved bits should be set to zero when programming the associated register. Note 14: With the exception of Standby Mode, rapid switching between modes should be avoided. Rapid switching between modes will not ensure that the desired mode will be activated. Note 15: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 16: 0dBm0 = -3dBFS for the PCM voice codec and 0dBm0 = -1dBFS for the I2S DAC, unless otherwise specified. www.national.com 15 |
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