Pin Descriptions (Continued)

F2

LS+

Loudspeaker amplifier BTL positive out (+)

F3

AVDD_LS

Analog V

F4

DGND_X

Digital ground

F5

DVDD_X

Digital V

DD

F6

MCLK/XTAL_IN

12.288MHz or 24.576MHz Master Clock from crystal (via XTAL OUT) or external source

SYSTEM CONTROL REGISTERS

The LM4930 is controlled with a two-wire serial interface. This interface is used to configure the operating mode, digital interfaces,

and delta-sigma modulators. The LM4930 is controlled by writing information into a series of write-only registers, each with its own

unique 7 bit address. The following registers are programmable:

Basic Config Register

This register is used to configure the I

BASICCONFIG register is XX10000.

(X=0if ADDR is set to logic 0)

(X=1if ADDR is set to logic 1)

BASIC CONFIGURATION (XX1000).

(Set = logic 1, Clear = logic 0)

BIT

15

14

13

12

11

10

987654321

0

RESET

0

0

0000000000000

0

Address

Register

Description

3:0

MODE

The LM4930 can be placed in one of several modes that dictate the basic operation. When a

new mode is selected the LM4930 will change operation silently and will reconfigure the

power management profile automatically. The modes are described as follows: (Note 14)

Mode

Mono Speaker

Amplifier Source

Headphone Left

Source

Headphone Right

Source

Comment

0000

None

None

None

Powerdown mode

0001

None

None

None

Standby Mode

0010

Voice

None

None

Mono speaker

mode

0011

None

Voice

Voice

Headphone call

mode

0100

Voice

Voice

Voice

Conference call

mode

0101

Audio (L+R)

None

None

L+R mixed to

mono speaker

0110

None

Audio (Left)

Audio (Right)

Headphone

stereo audio

0111

Audio (L+R)

Audio (Left)

Audio (Right)

L+R mixed to

mono speaker +

stereo headphone

audio

1000

Audio (Left)

Voice

Voice

Mixed Mode

1001

Voice + Audio

(Left)

Voice

Voice

Mixed mode

1010

Voice

Audio (Left)

Audio (Left)

Mixed Mode

4

SOFT_RESET

Resets the LM4930, excluding the control registers

5

PCM_LONG

If set the PCM interface uses a long frame sync. (Note 12)

6

PCM_COMPANDED

If set the 8 MSBs are presumed to be companded data and the 8 LSBs are ignored. (Note

12)

7

PCM_LAW

If set, the companded G711 data is set to be A-law, else m-law is assumed (Note 12)

8:9

PCM_SYNC_MODE

Sets 1 (00h), 2 (01h) or 4(10h) 16 bit frames per sync. The PCM_SDO pin is tri-stated during

the latter frames. (Note 12)

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