LM4930 datasheet(31/33 Pages) NSC

31 / 33 page

Application Information (Continued)

for the bus. It operates at a fixed frequency of 8kHz and may

be set in the BASICCONFIG register (bit 5 PCM_LONG) for

short or long frame sync. A short frame sync is 1 PCM_CLK

cycle (PCM_LONG=0), a long frame sync is 2 PCM_CLK

cycles long (PCM_LONG=1). A long sync pulse is also de-

layed one clock cycle relative to a short sync pulse. This is

illustrated in Figure 3. PCM_CLK is the bit clock for the bus.

It’s frequency depends on the number of 16-bit frames per

sync pulse and can be 128kHz, 256kHz, 512kHz.

The other two lines, PCM_SDO and PCM_SDI, are for serial

data out and serial data in, respectively. The type of data

may also be set in the BASICCONFIG register by bits 6 and

7. Bit 6 controls whether the data is linear or companded. If

set to 1, the 8 MSBs are presumed to be companded data

and the 8 LSBs are ignored. If cleared to 0, the data is

treated as 2’s complement PCM data. Bit 7 controls which

PCM law is used if Bit 6 is set for companded (G711) data. If

set to 1, the companded data is assumed to be A-law. If

cleared to 0, the companded data is treated as µ-law.

Bits 8:9 of the BASICCONFIG register set the PCM_SYNC-

_MODE settings. This controls the number of 16 bit frames

per sync pulse. The feature allows the LM4930 to function

harmoniously with other devices or channels on the PCM

bus by adjusting the number of 16 bit frames per sync pulse

to 1 (00b), 2 (01b), or 4 (10b). The LM4930 will transmit PCM

data in the first frame and then tri-state the PCM_SDO pin on

later frames.

In addition, the LM4930 provides control to allow the PCM-

_CLK and PCM_SYNC clocks to continue functioning even

when the LM4930 is in Standby mode. By setting bit 10 of

the BASICCONFIG register to 1 PCM_ALWAYS_ON is en-

abled and the LM4930 will continue to drive the PCM clock

and sync lines when in Standby mode. This bit should be set

if another codec is using the PCM bus. Powerdown mode

will disable these outputs.

I2S Interface Bus (J2)

The I2S standard provides a uni-directional serial interface

designed specifically for digital audio. For the LM4930, the

interface provides access to a 48kHz, 16 bit full-range stereo

audio DAC. This interface uses a three port system of clock

(I2S_CLK), data (I2S_DATA), and word (I2S_WS). The clock

and word lines can be either master or slave as set by bit 11

in the BASICCONFIG register.

A bit clock (I2S_CLK) at 32 or 64 times the sample frequency

is established by the I2S system master and a word select

(I2S_WS) line is driven at a frequency equal to the sampling

rate of the audio data, in this case 48kHz. The word line is

registered to change on the negative edge of the bit clock.

The serial data (I2S_DATA) is sent MSB first, again regis-

tered on the negative edge of the bit clock, delayed by 1 bit

clock cycle relative to the changing of the word line (typical

I2S format - see Figure 4).

The resolution of the I2S interface may be set by modifying

the I2S_RES bit (bit 12) in the BASICCONFIG register. If set

to 1, the LM4930 operates at 32 bits per frame (3.072MHz).

If cleared to 0, then 16 bits per frame is selected

(1.536MHz). This has a corresponding effect on the bit clock.

The I2S Interface Bus also provides for an additional MCLK

connection to an external device from the LM4930 demo

board. This may be used in conjunction with National Semi-

conductors SPDIF->I2S Conversion Board for quick evalu-

ation. This board features a connection header that inter-

faces with pins 1-5 of the I2S Interface Bus. Pins 6-10 are

provided as digital ground references for the case of discrete

connections.

MCLK/XTAL_IN (P5)

This is the input for an external Master Clock. The jumper at

S2 must be removed (disconnecting the onboard crystal

from the circuit) when using an external Master Clock.

BTL Mono Out (J7)

This is the mono speaker output, designed for use with an 8

ohm speaker. The outputs are driven in bridge-tied-load

(BTL) mode, so both sides have signal. Outputs are normally

biased at one half AVDD when the LM4930 is in active mode.

Additionally, if the CLASS bit is set to 1 in the VOICETEST-

CONFIG register (bit 0) the BTL mono output is internally

configured as a buffer amplifier designed for use with an

external class D amp.

Stereo Headphone Out (J8)

This is the stereo headphone output. Each channel is single-

ended, with 220uF DC blocking capacitors mounted on the

demo board. The jack features a typical stereo headphone

pinout.

A headphone sense pin is provided at J6. This pin provides

a clean logic high or low output to indicate the presence of

headphones in the headphone jack. A common application

circuit for this is given in the Reference Board Schematic

shown in Figure 5. In this application HPSENSE_IN is pulled

low by the 1k ohm resistor when no headphone is present.

This gives a corresponding logic low output on the

HPSENSE_OUT pin. When a headphone is placed in the

jack the 1k ohm pull-down is disconnected and a 100k ohm

pull-up resistor creates a high voltage condition on

HPSENSE_IN. This in turn creates a logic high on

HPSENSE_OUT. This output may be used to reliably drive

an external microcontroller with headphone status.

MIC Jack (J3)

This jack is for connection to an external microphone like the

kind typically found in mobile phones. Pin 1 is GND, pin 2 is

the negative input pin, and pin 3 is the positive pin, with

phantom voltage supplied by MIC_BIAS on the LM4930.

IRQ (J4)

This pin provides simple status updates from the LM4930 to

an external microcontroller if desired. IRQ is logic high when

the LM4930 is in a stable state and changes to low when

changing modes. This can also be useful for simple

software/driver development to monitor mode changes, or as

a simple debugging tool.

BASIC OPERATION

The LM4930 is a highly integrated audio subsystem with

many different operating modes available. These modes

may be controlled in the BASICCONFIG register in bits 3:0.

These mode settings are shown in the BASICCONFIG reg-

ister table and are described here below:

Powerdown Mode (0000b)

Part is powered down, analog outputs are not biased. This is

a minimum current mode. All part features are shut down.

LM4930 Datasheet(PDF) 31 Page - National Semiconductor (TI)

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