SX20AC75 datasheet(27/52 Pages) ETC

27 / 52 page

- 27 -

www.scenix.com

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

12.0

RESET

Power-On-Reset, Brown-Out reset, watchdog reset, or

external reset initializes the device. Each one of these

reset conditions causes the program counter to branch to

the top of the program memory. For example, on the

device with 2048K words of program memory, the pro-

gram counter is initialized to 07FF.

The device incorporates an on-chip Power-On Reset

(POR) circuit that generates an internal reset as Vdd rises

during power-up. Figure 12-1 is a block diagram of the

circuit. The circuit contains an 10-bit Delay Reset Timer

(DRT) and a reset latch. The DRT controls the reset time-

out delay. The reset latch controls the internal reset sig-

nal. Upon power-up, the reset latch is set (device held in

reset), and the DRT starts counting once it detects a valid

logic high signal at the MCLR pin. Once DRT reaches the

end of the timeout period (typically 72 msec), the reset

latch is cleared, releasing the device from reset state.

Figure 12-2 shows a power-up sequence where MCLR is

not tied to the Vdd pin and Vdd signal is allowed to rise

and stabilize before MCLR pin is brought high. The

device will actually come out of reset Tdrt msec after

MCLR goes high.

The brown-out circuitry resets the chip when device

power (Vdd) dips below its minimum allowed value, but

not to zero, and then recovers to the normal value.

Note:Ripple counter is 10 bits for Power on Reset (POR)

only.

Figure 12-1. Block Diagram of On-Chip Reset Circuit

POR

BROWN-OUT

MIWU

MCLR/Vpp pin

wdt_time_out

10-Bit Asynch

Ripple

Counter

(DRT Start-Up

Timer)

Vdd

rc_clk

drt_time

_out

RESET

POR

enable

Figure 12-2. Time-Out Sequence on Power-Up

(MCLR not tied to Vdd)

Vdd

MCLR

POR

drt_time_out

RESET

Tdrt

SX20AC75 Datasheet(PDF) 27 Page - List of Unclassifed Manufacturers

SX20AC75 Datasheet(HTML) 27 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL