SX20AC75 datasheet(34/52 Pages) ETC

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

15.13

Comparison and Conditional Branch

Instructions

The instruction set includes instructions such as DECSZ

fr (decrement file register and skip if zero), INCSZ fr

(increment file register and skip if zero), SNB bit (bit test

file register and skip if bit clear), and SB bit (bit test file

the next instruction to be skipped if the tested condition is

true. If a skip instruction is immediately followed by a

PAGE or BANK instruction (and the tested condition is

true) then two instructions are skipped and the operation

consumes three cycles. This is useful for conditional

branching to another page where a PAGE instruction pre-

cedes a JMP. If several PAGE and BANK instructions

immediately follow a skip instruction then they are all

skipped plus the next instruction and a cycle is consumed

for each.

15.14

Logical Instruction

The instruction set contain a full complement of the logi-

cal instructions (AND, OR, Exclusive OR), with the W

direct or indirect addressing) serving as the two oper-

ands.

15.15

Shift and Rotate Instructions

The instruction set includes instructions for left or right

rotate-through-carry.

15.16

Complement and SWAP

The device can perform one’s complement operation on

the file register (fr) and W register. The MOV W,<>fr

instruction performs nibble-swap on the fr and puts the

value into the W register.

15.17

Key to Abbreviations and Symbols

Symbol

Description

Working register

File register (memory-mapped register in the

range of 00h to FFh)

Lower eight bits of program counter (file regis-

ter 02h)

STATUS

STATUS register (file register 03h)

FSR

File Select Register (file register 04h)

Carry bit in STATUS register (bit 0)

Digit Carry bit in STATUS register (bit 1)

Zero bit in STATUS register (bit 2

Power Down bit in STATUS register (bit 3)

Watchdog Timeout bit in STATUS register (bit

PA2:PA0

Page select bits in STATUS register (bits 7:5)

OPTION

OPTION register (not memory-mapped)

WDT

Watchdog Timer register (not memory-

mapped)

MODE

MODE register (not memory-mapped)

Port control register pointer (RA, RB, or RC)

Non-memory-mapped register designator

File register address bit in opcode

Constant value bit in opcode

Numerical value bit in opcode

Bit position selector bit in opcode

File register / bit selector separator in assem-

bly language instruction

Immediate literal designator in assembly lan-

guage instruction

lit

Literal value in assembly language instruction

addr8

8-bit address in assembly language instruction

addr9

9-bit address in assembly language instruction

addr12

12-bit address in assembly language instruc-

tion

Logical 1’s complement

Logical OR

Logical exclusive OR

Logical AND

Swap high and low nibbles (4-bit segments)

Rotate left through carry bit

Rotate right through carry bit

- -

Decrement file register

Increment file register

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