P83CX80 datasheet(28/84 Pages) PHILIPS

28 / 84 page

1997 Dec 12

Philips Semiconductors

Product speciﬁcation

Microcontrollers for monitors with DDC

interface, auto-sync detection and sync proc.

P83Cx80; P87C380

Fig.11 On-chip reset configuration.

handbook, full pagewidth

MGG022

SCHMITT

TRIGGER

RESET

CIRCUITRY

RRESET

overflow timer T2

Power-on-reset

RSTOUT

8 k

Ω

µF

VDD

on-chip circuit

RESET

POC

13.1

External reset

Pin RESET is connected to a Schmitt trigger for noise

reduction (see Fig.11). A reset is accomplished by holding

the RESET pin HIGH for at least 16 machine cycles (192

system clocks) while the oscillator is running.

An automatic reset can be obtained by switching on VDD,

if the RESET pin is connected to VDD via a capacitor and

a resistor as illustrated in Fig.11. The VDD rise time must

not exceed 10 ms and the capacitor should be at least

µF. The decrease of the RESET pin voltage depends

on the capacitor and the external resistor RRESET. The

voltage must remain above the lower threshold for at least

the oscillator start-up time plus 2 machine cycles.

13.2

Power-on-reset

An on-chip Power-on-reset circuit that detects the supply

voltage rise or fall and accordingly generates a power-on

reset pulse (see Fig.12).

In the case of supply voltage rise, the power-on reset

signal will follow the supply voltage rise; after reaching the

trip level Vt the power-on reset signal will maintain the

same behaviour, and returns to a LOW state after a time

interval Tp.

In the case of supply voltage fall, after the trip level Vt is

reached, the power-on reset signal will follow the

waveform of the supply voltage for time interval Tp.

The time interval Tp guarantees that a complete power-on

reset pulse can trigger the internal reset signal. However,

to ensure that the oscillator is stable before the controller

starts, the clock signals are gated away from the CPU for

a further 2048 oscillator cycles.

The values of Vt, Tp and a process tolerance of ±∆Vt can

be found in Chapter 25; currently Vt = 3.9 V, Tp =10 µs

and

∆Vt = 0.3 V.

13.3

T2 (Watchdog Timer Data Register) overﬂow

The length of the output pulse from T2 is 3 machine cycles.

A pulse of such short duration is necessary in order to

recover from a processor or system fault as fast as

possible.

P83CX80 Datasheet(PDF) 28 Page - NXP Semiconductors

P83CX80 Datasheet(HTML) 28 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Datasheet Download

Link URL