P83C180 datasheet(49/84 Pages) PHILIPS

49 / 84 page

1997 Dec 12

Philips Semiconductors

Product speciﬁcation

Microcontrollers for monitors with DDC

interface, auto-sync detection and sync proc.

P83Cx80; P87C380

17.5

DDC2AB/DDC2B+ protocol

DDC2AB/DDC2B+ is a superset of DDC2B. Monitors that

implement DDC2AB/DDC2B+ are full featured

ACCESS.bus devices. Essentially, they are similar to

DDC2B. The I2C-bus interface forms the fundamental

layer for both protocols. However, in DDC2AB/DDC2B+

the default address for monitors is assigned to 6EH

instead of A0H and A1H in DDC2B. Monitors and hosts

can play both the roles of master and slave. Under this

kind of protocol, it is easy to extend the support for hosts

to read VESA Video Display Information Format (VDIF)

and remotely control monitor functions.

The read/write protocols can be the same as described in

Section 17.4.

Nevertheless, the command/information sequence

between host and monitor must conform to the

specification of ACCESS.bus.

Timing rules specified in ACCESS.bus such as maximum

response time to RESET message (<250 ms) from host,

maximum time to hold SCL LOW (<2 ms) etc., can be

satisfied through software checks and built-in timers such

as Timer 0 and Timer 1 in the P83C880. In

DDC2AB/DDC2B+ the monitor itself can act as a master to

activate the transaction. The default address assigned for

the host is 50H.

Figure 26 shows the overview and relationship between

software and the existing I2C-bus hardware for the DDC

interface.

Fig.26 The conceptual structure of the DDC interface.

handbook, full pagewidth

MGG035

DDC INTERRUPT

VECTOR ADDRESS

(002BH)

MODE = 1

CHECK MODE FLAG IN DDCCON

MODE = 0

DDC2B

+/DDC2AB

COMMAND

RECEIVED

DDC2B

COMMAND

RECEIVED

DDC2B

+/DDC2AB

UTILITIES

DDC2B

UTILITIES

I2C-BUS

SERVICE ROUTINES

DDC1

UTILITIES

I2C-BUS INTERFACE

(HARDWARE)

DDC1 TRANSMITTER

(HARDWARE)

SWENB = 0

SWENB = 1

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