P83C180 datasheet(19/84 Pages) PHILIPS

19 / 84 page

1997 Dec 12

Philips Semiconductors

Product speciﬁcation

Microcontrollers for monitors with DDC

interface, auto-sync detection and sync proc.

P83Cx80; P87C380

8.2

How interrupts are handled

The interrupt flags are sampled at the S5P2 state of every

machine cycle. The samples are polled during the

following machine cycle. If one of the flags was in a set

condition at S5P2 of the preceding cycle, the polling cycle

will find it and the interrupt system will generate an LCALL

to the appropriate service routine, provided this hardware

generated LCALL is not blocked by any of the following

conditions:

1. An interrupt of equal priority or higher priority level is

already in progress.

2. The current (polling) cycle is not the final cycle in the

execution of the instruction in progress.

3. The instruction in progress is RETI or any write to the

IE or IP registers.

Any of these conditions will block the generation of the

LCALL to the interrupt service routine. Condition 2

ensures that the instruction in progress will be completed

before vectoring to any service routine.

Condition 3 ensures that if the instruction in progress is

RETI or any access to IE or IP, then at least one more

instruction will be executed before the interrupt is vectored

to.The polling cycle is repeated with each machine cycle,

and the values polled are the values that were present at

S5P2 of the previous machine cycle. Note that if an

interrupt flag is active but not being responded to for one

of the above mentioned conditions, and if the flag is still

inactive when the blocking condition is removed, then the

denied interrupt will not be serviced. In other words, the

fact that the interrupt flag was once active but not serviced

is not remembered. Every polling cycle is new.

The polling cycle/LCALL sequence is illustrated in

“Data

Handbook IC20; 80C51 family hardware description;

Figure: Interrupt Response Timing Diagram”.

Note that if an interrupt of higher priority level becomes

active prior to S5P2 of the machine cycle labelled C3 (see

“Data Handbook IC20; 80C51 family hardware description;

Figure: Interrupt Response Timing Diagram”), then in

accordance with the above rules it will be vectored to

during C5 and C6, without any instruction of the lower

priority routine having been executed. Thus the processor

acknowledges an interrupt request by executing a

hardware generated LCALL to the appropriate servicing

routine. The hardware generated LCALL pushes the

contents of the Program Counter on to the stack (but it

does not save the PSW) and reloads the PC with an

address that depends on the source of the interrupt being

vectored to as shown in Table 22.

Execution proceeds from that location until the RETI

instruction is encountered. The RETI instruction informs

the processor that the interrupt routine is no longer in

progress, then pops the top two bytes from the stack and

reloads the Program Counter. Execution of the interrupted

program continues from where it left off.

Note that a simple RET instruction would also return

execution to the interrupted program, but it would have left

the interrupt control system thinking an interrupt was still in

progress, making future interrupts impossible.

Table 22 Vector addresses

SOURCE

VECTOR ADDRESS

IE0

′

0003H

002BH

TF0

000BH

IE1

′

0013H

TF1

001BH

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