ML6652 datasheet(8/28 Pages) MICRO-LINEAR

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ML6652

January 2002

Preliminary Datasheet

PIN DESCRIPTIONS (continued)

Pin No. Signal Name

I/O

Description

CONTROL

TPOUTOFF#

I (CMOS)

Active low, the output stage of the twisted pair output is turned off. If not

connected they are pulled high by internal resistors

FOOUTOFF#

I (CMOS)

Active low, the output stage of the fiber optic output is turned off. If not

connected they are pulled high by internal resistors

PWRDWN#

I (CMOS)

Active low, all the circuits are powered down. Configuration pins are read and

µs after a rising edge of PWRDWN#. If not

connected they are pulled high by internal resistors

DATA SIGNAL INPUT/OUTPUT

TPOUTP

The two operating modes available for these pins are selected with the

configuration pin PECLTP (pin 7) or the configuration bit PECLTP <30.3>

TPOUTN

Twisted Pair Interface Mode:

Transmit twisted pair positive and complementary outputs. These outputs form

a differential current output pair that drives Multi Level Transition (MLT-3)

waveforms into the network coupling transformer during 100Mbps mode,

Manchester encoded 10Base-T data or Normal Line Pulses (NLPs) during

10Mbps mode, and Fast Link Pulse (FLP) Bursts during Auto-Negotiation.

TPOUTP and TPOUTN must have external pull up resistors to VCC (refer to

description of RTTP pin)

PECL/LVPECL Compatible Interface Mode:

PECL/LVPECL interface positive and complementary outputs. These outputs

form a differential current output pair that drives Non Return to Zero Inverted

(NRZI) encoded 100Base-FX or 100Base-SX symbols during 100Mbps mode,

Manchester encoded 10Base-FL data or OPT_IDL during 10Mbps mode, and

Fiber Link Negotiation Pulse (FLNP) Bursts during Auto-Negotiation. TPOUTP

and TPOUTN must have external pull up resistors to VCC and be AC coupled

to the inputs of a fiber optic PMD module (refer to description of RTTP pin). A

resistor network may be needed to setup the common mode voltage at the

input pins of the PMD module

RTTP

Twisted pair PECL/LVPECL compatible driver bias resistor. An external resistor

connected between RTTP and ground sets a constant bias current for the

differential output driver circuitry TPOUTP/TPOUTN.

These output currents depend on the operating mode.

The recommended external component values are:

Twisted Pair Mode:

Ω, 1%, between RTTP and ground

Ω, 1%, between TPOUTP and VCC

Ω, 1%, between TPOUTN and VCC

PECL Compatible mode:

Ω, 1%, between RTTP and ground

Ω, 1%, between TPOUTP and VCC

Ω, 1%, between TPOUTN and VCC

Also AC coupled to the PMD inputs

TPINP

The two operating modes available for these pins are selected with the

configuration pin PECLTP (Pin 7) or the configuration bit PECLTP <30.3>.

TPINN

Twisted Pair Interface Mode:

Receive twisted pair positive and complementary inputs. These inputs form a

differential input pair that receives 100Base-TX, FLP Burst, or 10Base-T signal

from the network. The common mode voltage is set internally and the

differential input resistance is about 2K

Ω.

The twisted pair interface requires a network consisting of a 1500Pf capacitor

and a 200

Ω resistor in parallel; in series with each pin 10 and 11 as shown in

Figure 1.

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