ML6652 datasheet(11/28 Pages) MICRO-LINEAR

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ML6652

January 2002

Preliminary Datasheet

PIN DESCRIPTIONS (continued)

Pin No. Signal Name

I/O

Description

SDFO

The two operating modes available for this pin are selected with the

configuration pin PECLQU or the configuration bit PECLQU <30.2>

Fiber Optic Interface Mode:

This pin is not used and should be connected to VCC.

PECL/LVPECL Compatible Interface Mode:

This input pin is connected to the Signal Detect (SD) output of a fiber optic

PMD. The voltage level at this pin is compared to the voltage level at pin

SDTH to determine the logic value. If it is lower than the input at FOINP/

FOINN is rejected. If it is higher than the input at FOINP/FOINN is passed to

the internal circuits.

BACKUP LINK FUNCTION

BCKPLINK

I/O

INPUT MODE:

At power up, pin 40 (BCKPLINK) is read and the BCKPDIS register <28.1> is set

appropriately. A high (VCC) at power up causes Register 28, Bit 1 (BCKPDIS)

to be set high (1) disabling the Back-up link function. BCKPDIS can

subsequently be over written by the management interface at any time.

Note: This pin is typically read a few microseconds after power-up, if it is tied

to supplies that do not track the ML6652 power, improper results may occur.

For BCKPLINK, use VCCD (pin 19) as the pull up point, do not add decoupling

capacitors to Pin 40 (without thoroughly understanding your PCB layout power

up dynamics the safest course is to make short connections and do not add

decoupling capacitors to this pin).

OUTPUT MODE:

After power-up, BCKPLINK is used as an output. It is Active high to enable a

secondary fiber link via a second ML6652 device (see Functional Description,

Backup Link Mode in this data sheet for details).

Use this function in forced 100Mbps mode, non loopback only

LED STATUS

TPINSPD

This output goes high to indicate that a 100Mbps signal is present at the TPINP/

TPINN interface, and it goes low to indicate that a 10Mbps signal is present at

the TPINP/TPINN interface. The signal can be idle or packets. This pin is set to

high impedance otherwise.

FOINSPD

This output goes high to indicate that a 100Mbps signal is present at the

FOINP/FOINN interface, and it goes low to indicate that a 10Mbps signal is

present at the FOINP/FOINN interface. The signal can be idle or packets. This

pin is set to high impedance otherwise.

TPANDT

When TPINSPD is in the high impedance state, no 10 or 100Mbps signal at

TPINP/TPINN, the TPANDT LED pulls low while receiving Auto-Negotiation

signal at the TPINP/TPINN interface. When TPINSPD is not in the high

impedance state, the TPANDT pin pulls low to indicate that a data packet is

being detected at the TPINP/TPINN interface. When a data packet is indicated,

the pulse width at TPANDT is stretched to a minimum of 1.3 to 2.7ms to

improve visibility. This low current LED driver interface requires a 10K

Ω pull-

up resistor and a small CMOS buffer as shown in Figure 2. In any other case

this pin is in high impedance state.

10K

Ω

TPAN_DT

VCCD

560

Ω

TPAN_DT

LED

CMOS Buffer, Fairchild NC7WZ16 or Equivalent,

Buffer VCC=VCCD, Buffer Ground = DGND

Figure 2.

ML6652 Datasheet(PDF) 11 Page - Micro Linear Corporation

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