LMX9820 datasheet(6/40 Pages) NSC

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5.0 Pad Descriptions (Continued)

Table 5. Auxiliary Ports Interface Signals

Pad Name

Pad

Location

Direction

Description

IOVCC

H12

Input

2.85V to 3.6V Logic Threshold Program Input.

Reset_b#

Input

Reset Input for Smart Radio. Normally connected to Reset_5100.

Reset_5100#

D11

Input

Reset for Baseband and Link Management Processors. Active

low.

Lstat_0

Output

Link Status Bit 0.

Lstat_1

Output

Link Status Bit 1.

Host_wu

Output

Host Wakeup

Env0

Input

Module Operating Environment Bit 0.

Env1

B11

Input

Module Operating Environment Bit 1.

TX_Switch_P

Output

Transceiver Status, 0 = Receive; 1 = Transmit.

Table 6. Audio Port Interface Signals (not supported by LMX9820 Firmware)

Pad Name

Pad

Location

Direction

Description

AAI_srd

B10

Input

Advanced Audio Interface Receive Data Input.1

AAI_std

B12

Output

Advanced Audio Interface Transmit Data Output.1

AAI_sfs

C11

Input/Output

Advanced Audio Interface Frame Synchronization.1

AAI_sclk

C12

Input/Output

Advanced Audio Interface Clock.1

Treat as No Connect, Pad required for mechanical stability.

Table 7. Test Interface Signals

Pad Name

Pad

Location

Direction

Description

J_rdy

E10

Output

JTAG Ready.1

J_tdi

F10

Input

JTAG Test Data.1

J_tdo

F11

Input/Output

JTAG Test Data.1

J_tms

Input/Output

JTAG Test Mode Select.1

J_tck

G10

Input

JTAG Test Clock. 1

PI1_RFCE_TP1

Testpin

Module Test Point.1

PI2_TP12

A13

Testpin

Module Test Point.1

Tx_rx_clock

Testpin

Module Test Point.1

Tx_rx_data

Testpin

Module Test Point.1

Tx_rx_synch

A10

Testpin

Module Test Point.1

CCB_Clock

A11

Testpin

Module Test Point.1

CCB_data

Testpin

Module Test Point.1

CCB_latch

J12

Testpin

Module Test Point.1

BBCLK

A12

Testpin

Module Test Point.1

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