HMC701LP6CE datasheet(21/40 Pages) AD

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HMC701LP6CE

v09.1112

8 GHz 16-BIT FRACTIONAL-N PLL

Frequency Hopping Trigger

if the synthesizer is in fractional mode, a write to the fractional frequency register, Reg10h table 27, will initiate the

frequency hop on the falling edge of the 31st clock edge of the serial port write (see Figure 19).

if the integer frequency register, Reg0Fh table 26, is written when in fractional mode the information will be buffered

and only executed when the fractional frequency register is written.

if the synthesizer is in integer mode, a write to the integer frequency register, Reg0Fh table 26, will initiate the

frequency hop on the falling edge of the 31st clock edge of the serial port write (see Figure 19).

Power On Reset (POR)

normally all logic cells in the HMc701LP6cE are reset when the device digital power supply, DVDD, is applied. this

is referred to as Power on reset, or just Por. Por normally takes about 500us after the DVDD supply exceeds 1.5V,

guaranteed to be reset in 1msec. once the DVDD supply exceeds 1.5V, the Por will not reset the digital again unless

the supply drops below 100mV.

Soft Reset

the SPi registers may also be soft reset by an SPi write to strobe global_swrst_regs (Reg00h<0> table 11).

all other digital, including the fractional modulator, may be reset with an SPi write to strobe global_swrst_dig

(Reg00h<1> table 11).

Hardware Reset

the SPi registers may also be hardware reset by holding rStB, pin 19, low.

Power Down

the HMc701LP6cE may be powered down by writing a zero to Reg01h table 12. in power down state the

HMc701LP6cE should draw less than 10ua. it should be noted that Reg01h is the Enable and reset register which

controls 16 separate functions in the chip. Depending upon the desired mode of operation of the chip, not all of the

functions may be enabled when in operation. Hence power up of the chip requires a selective write to Reg01 bits. an

easy way to return the chip to its prior state after a power down is to first read Reg01h and save the state, then write a

zero to Reg01h for reset and then simply rewrite the previous value to restore the chip to the desired operating mode.

CW Sweeper Mode

the HMc701LP6cE features a built in frequency sweeper function. this function supports external or automatic

triggered sweeps. the maximum sweep range is limited to 255 x Fxtal/r. For example, with a 25 MHz comparison

frequency, the maximum sweep range is 6375 MHz. the start and end frequency points must be within 6375 MHz of

one another. For sweep operation the Delta-Sigma Modulator mode should be Feed Forward (register 12h Bits [9:8]

= 11) otherwise discontinuities may occur when crossing integer-n boundaries (harmonic multiples of the comparison

frequency).

Sweeper Modes include:

a. 2-Way Sweep Mode: alternating positive and negative frequency ramps.

b. 1-Way Sweep Mode

c. Single Step ramp Mode

applications include test instrumentation, FMcW sensors, automotive radars and others. the parameters of the

sweep function are illustrated in Figure 15.

the sweep generator is enabled with ramp_enable in (Reg14h<1> table 30). the sweep function cycles through a

series of discrete frequency values, which may be

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rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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