LM78 datasheet(16/31 Pages) NSC

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Functional Description (Continued)

3.0 USING THE LM78

3.1 Power On

When power is first applied, the LM78 performs a “power on

reset” on several of its registers. The power on condition of

registers in shown in Table I. Registers whose power on

values are not shown have power on conditions that are

indeterminate (this includes the value RAM and WATCH-

DOG limits). The ADC is inactive. In most applications, usu-

ally the first action after power on would be to write WATCH-

DOG limits into the Value RAM.

3.2 Resets

Configuration Register INITIALIZATION accomplishes the

same function as power on reset on most registers. The

POST RAM, Value RAM conversion results, and Value RAM

WATCHDOG limits are not Reset and will be indeterminate

immediately after power on. If the Value RAM contains valid

conversion results and/or Value RAM WATCHDOG limits

have been previously set, they will not be affected by a

Configuration Register INITIALIZATION. Power on reset, or

Configuration Register INITIALIZATION, clear or initialize

the following registers (the initialized values are shown on

Table I):

•

Configuration Register

•

Interrupt Status Register 1

•

Interrupt Status Register 2

•

SMI Mask Register 1

•

SMI Mask Register 2

•

NMI Mask Register 1

•

NMI Mask Register 2

•

VID/Fan Divisor Register

•

Serial Bus Address Register (Power on reset only, not

reset by Configuration Register INITIALIZATION)

Configuration Register INITIALIZATION is accomplished by

setting Bit 7 of the Configuration Register high. This bit

automatically clears after being set.

The LM78-J allows the user to perform an unconditional

complete Power-on reset by writing a one to Bit 5 of the Chip

Reset/ID Register. The LM78-J can be differentiated from

the LM78 without the J suffix by reading Chip Reset/ID

used. The LM78-J allows an unconditional complete

Power-on reset to be initiated by taking the IOWR and IORD

signal lines low simultaneously, for at least 50 ns, while CS is

high. The delay between consecutive IORD and IOWR

pulses should be greater than 50 ns to ensure that an

Power-on reset does not occur unintentionally.

In systems where the serial bus is only being used it may be

advantageous to take both IOWR and IORD to the system

reset pulse. In this way whenever the system is reset the

LM78-J will also be reset to a known state.

3.3 Using the Configuration Register

The Configuration Register provides all control over the

LM78. At power on, the ADC is stopped and INT__Clear is

asserted, clearing the SMI and NMI/IRQ hardwire outputs.

The Configuration Register starts and stops the LM78, en-

ables and disables interrupt outputs and modes, and pro-

vides the Reset function described in Section 3.2.

Bit 0 of the Configuration Register controls the monitoring

loop of the LM78. Setting Bit 0 low stops the LM78 monitor-

ing loop and puts the LM78 in shutdown mode, reducing

power consumption. ISA and Serial Bus communication is

possible with any register in the LM78 although activity on

these lines will increase shutdown current, up to as much as

maximum rated supply current, while the activity takes place.

Taking Bit 0 high starts the monitoring loop, described in

more detail subsequently.

Bit 1 of the Configuration Register enables the SMI Interrupt

hardwire output when this bit is taken high. Similarly, Bit 2 of

the Configuration Register enables the NMI/IRQ Interrupt

hardwire output when taken high. The NMI/IRQ mode is

determined by Bit 5 in the Configuration Register. When Bit

5 is low the output is an active low IRQ output. Taking Bit 5

high inverts this output to provide an active high NMI output.

The Power Switch Bypass provides an active low at the

Power Switch Bypass output when set high. This is intended

for use in software power control by activating an external

power control MOSFET.

3.4 Starting Conversion

The monitoring function (Analog inputs, temperature, and

fan speeds) in the LM78 is started by writing to the Configu-

ration Register and setting INT__Clear (Bit 3), low, and Start

(bit 0), high. The LM78 then performs a “round-robin” moni-

toring of all analog inputs, temperature, and fan speed inputs

approximately once a second. The sequence of items being

monitored corresponds to locations in the Value RAM and is:

Temperature

IN0

IN1

IN2

IN3

IN4

-IN5

-IN6

Fan 1

10. Fan 2

11. Fan 3

3.5 Reading Conversion Results

The conversion results are available in the Value RAM.

Conversions can be read at any time and will provide the

result of the last conversion. Because the ADC stops, and

starts a new conversion whenever it is read, reads of any

single value should not be done more often then once every

120 ms. When reading all values, allow at least 1.5 seconds

between reading groups of values. Reading more frequently

than once every 1.5 seconds can also prevent complete

updates of Interrupt Status Registers and Interrupt Output’s.

A typical sequence of events upon power on of the LM78

would consist of:

Set WATCHDOG Limits

Set Interrupt Masks

Start the LM78 monitoring process

4.0 ANALOG INPUTS

The 8-bit ADC has a 16 mV LSB, yielding a 0V to 4.08V

(4.096–1LSB) input range. This is true for all analog inputs.

In PC monitoring applications these inputs would most often

be connected to power supplies. The 2.5V and 3.3V supplies

can be directly connected to the inputs. The 5V and 12V

inputs should be attenuated with external resistors to any

desired value within the input range.

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