SDP User Guide

UG-277

Rev. B | Page 7 of 24

Pin No.

Pin Name

Description

51

NC

No Connect. Leave this pin unconnected. Do not ground.

52

GND

Connect to ground plane of board.

53

NC

No Connect. Leave this pin unconnected. Do not ground.

54

NC

No Connect. Leave this pin unconnected. Do not ground.

55

NC

No Connect. Leave this pin unconnected. Do not ground.

56

EEPROM_A0

EEPROM A0. Connect to A0 address line of the EEPROM.

57

RESET_OUT

Active low reset signal from processor board.

58

GND

Connect to ground plane of board.

59

UART_RX

UART Receive Data.2

60

RESET_IN

Active low pin to reset controller board.

61

BMODE1

Boot Mode 1. Pull up with 10 kΩ resistor to set SDP to boot from SPI Flash. Enabled on Connector A only.

62

UART_TX

UART Transmit Data2.

63

GND

Connect to ground plane of board.

64

SLEEP

Active low sleep from processor board.

65

WAKE

External wake up to processor board.

66

NC

No Connect. Leave this pin unconnected. Do not ground.

67

NC

No Connect. Leave this pin unconnected. Do not ground.

68

NC

No Connect. Leave this pin unconnected. Do not ground.

69

GND

Connect to ground plane of board.

70

NC

No Connect. Leave this pin unconnected. Do not ground.

71

CLKOUT

CLKOUT from processor.

72

TMR_D

Timer D Flag Pin.2

73

TMR_B

Timer B Flag Pin. Use as second timer, if required.

74

GPIO7

General-Purpose Input/Output.

75

GND

Connect to ground plane of board.

76

GPIO5

General-Purpose Input/Output.

77

GPIO3

General-Purpose Input/Output.

78

GPIO1

General-Purpose Input/Output.

79

SCL_0

80

SDA_0

81

GND

Connect to ground plane of board.

82

SPI_CLK

SPI Clock.

83

SPI_MISO

SPI Master In, Slave Out Data.

84

SPI_MOSI

SPI Master Out, Slave In Data.

85

SPI_SEL_A

SPI Chip Select A. Use this to control the first device on the SPI bus.

86

GND

Connect to ground plane of board.

87

SPORT_TSCLK

SPORT Transmit Clock.

88

SPORT_DT0

SPORT Data Transmit 0. Primary SPORT data from processor.

89

SPORT_TFS

SPORT Transmit Frame Sync.

90

SPORT_RFS

SPORT Receive Frame Sync.

91

SPORT_DR0

SPORT Data Receive 0. Primary SPORT data into processor.

92

SPORT_RSCLK

SPORT Receive Clock.

93

GND

Connect to ground plane of board.

94

PAR_CLK

Clock for Synchronous Parallel Interface (PPI).

95

PAR_FS2

Synchronous (PPI) Parallel Frame Sync 2.

96

PAR_A0

Parallel Address Bus Bit 0.

97

PAR_A2

Parallel Address Bus Bit 2.

98

GND

Connect to ground plane of board.

99

PAR_INT

Parallel Interrupt. Used to trigger a nonperiodic parallel event.

100

PAR_WR

Asynchronous Parallel Write Strobe.

101

PAR_D0

Parallel Data Bus Bit 0.

102

PAR_D2

Parallel Data Bus Bit 2.

103

PAR_D4

Parallel Data Bus Bit 4.