AD5432 datasheet(12/24 Pages) AD

12 / 24 page

REV. 0

–12–

AD5426/AD5432/AD5443

DAC SECTION

The AD5426, AD5432, and AD5443 are 8-, 10-, and 12-bit cur-

rent output DACs consisting of a standard inverting R-2R ladder

configuration. A simplified diagram for the 8-bit AD54246 is

shown in Figure 4. The feedback resistor RFB has a value of R.

The value of R is typically 10 k

Ω (minimum 8 kΩ and maximum

12 k

Ω). If IOUT1 and IOUT2 are kept at the same potential, a con-

stant current flows in each ladder leg, regardless of digital input

code. Therefore, the input resistance presented at VREF is always

constant and nominally of value R. The DAC output (IOUT) is

code-dependent, producing various resistances and capacitances.

External amplifier choice should take into account the variation

in impedance generated by the DAC on the amplifiers inverting

input node.

VREF

IOUT2

DAC DATA LATCHES

AND DRIVERS

IOUT1

RFB A

Figure 4. Simplified Ladder

Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals

of the DAC, making the device extremely versatile and allowing

it to be configured in several different operating modes, for

example, to provide a unipolar output, 4-quadrant multiplica-

tion in bipolar mode, or in single-supply modes of operation.

Note that a matching switch is used in series with the internal

RFB feedback resistor. If users attempt to measure RFB, power

must be applied to VDD to achieve continuity.

SERIAL INTERFACE

The AD5426/AD5432/AD5443 have an easy to use 3-wire inter-

face that is compatible with SPI/QSPI/MICROWIRE and DSP

interface standards. Data is written to the device in 16 bit words.

This 16-bit word consists of 4 control bits and either 8, 10, or

12 data bits as shown in Figure 5. The AD5443 uses all 12 bits of

DAC data. The AD5432 uses 10 bits and ignores the 2 LSBs,

while the AD5426 uses 8 bits and ignores the last 4 bits.

Low Power Serial Interface

To minimize the power consumption of the device, the interface

powers up fully only when the device is being written to, i.e., on

the falling edge of

SYNC. The SCLK and D

IN input buffers are

powered down on the rising edge of

SYNC.

DAC Control Bits C3 to C0

Control Bits C3 to C0 allow control of various functions of the

DAC as seen in Table I. Default settings of the DAC on power

on are as follows:

Data clocked into shift register on falling clock edges; daisy-chain

mode is enabled. Device powers on with zero-scale load to the

DAC register and IOUT lines.

The DAC control bits allow the user to adjust certain features

on power-on, for example, daisy-chaining may be disabled if not

in use, active clock edge may be changed to rising edge, and DAC

output may be cleared to either zero or midscale. The user may

also initiate a readback of the DAC register contents for verifi-

cation purposes.

Table I. DAC Control Bits

C3 C2 C1 C0

Function Implemented

0000

No Operation (Power-On Default)

0001

Load and Update

0010

Initiate Readback

0011

Reserved

0100

Reserved

0101

Reserved

0110

Reserved

0111

Reserved

1000

Reserved

1001

Daisy-chain Disable

1010

Clock Data to Shift Register On Rising Edge

1011

Clear DAC Output to Zero

1100

Clear DAC Output to Midscale

1101

Reserved

1110

Reserved

1111

Reserved

DB0 (LSB)

DB15 (MSB)

DATA BITS

CONTROL BITS

DB7 DB6 DB5 DB4

DB3 DB2

DB0

DB1

Figure 5a. AD5426 8-Bit Input Shift Register Contents

DB5 DB4

DB3 DB2

DB0

DB1

DB0 (LSB)

DB15 (MSB)

DATA BITS

CONTROL BITS

DB7 DB6

DB8

DB9

Figure 5b. AD5432 10-Bit Input Shift Register Contents

DB7 DB6 DB5 DB4 DB3 DB2

DB0

DB0 (LSB)

DB15 (MSB)

DATA BITS

DB1

DB11 DB10

DB8

DB9

CONTROL BITS

Figure 5c. AD5443 12-Bit Input Shift Register Contents

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