DATA TRANSFER EXAMPLE

The following routines based on the flowchart shown in

Fig-

code that can be used to control the LMC1992 (see Nation-

al Semiconductor’s COPS Microcontrollers Databook for

more information) These routines arbitrarily select COPS

register 0 for IO purposes When these routines are en-

tered it is assumed that chip select is high SK (clock) is

low and SO (data) is low These routines exit with chip se-

lect high and SK and SO low Output port G0 is arbitrarily

chosen to send the chip select signal to the LMC1992

The 11 data bits needed to control the LMC1992 are as-

sumed to be in the 4-bit registers 13 – 15 with the 4 MSBs

in register 13 With this configuration there is an extra bit for

a data stream that is 12 bits long As previously mentioned

there can be any number of extra bits between the device

address and the function address

DATA TRANSFER ROUTINE 1

This general purpose routine handles all the overhead ex-

cept loading data into registers 13 – 15 It sends the data

according to the conditions discussed above The data will

be lost at the conclusion of the routine This routine con-

sumes only 17 ROM memory locations

OUT1

LBI

013

POINT TO START OF DATA

WORD

SC

SET C TO ENABLE SK CLOCK

OGI

14

SELECT EXTERNAL DEVICE G0

4 0

LEI

8

ENABLE SHIFT REGISTER

OUTPUT

SEND

LD

XAS

DATA TRANSMISSION LOOP

XIS

TURN-ON CLOCK

JP

SEND

RC

OGI

15

DE-SELECT EXTERNAL

DEVICE

LEI

0

SET S0 TO 0

RET

DATA TRANSFER ROUTINE 2

This routine performs the same function as routine 1 while

preserving the contents of the data registers This routine

takes only 21 ROM memory locations

OUT1

LBI

013

POINT TO START OF DATA

WORD

SC

SET C TO ENABLE SK CLOCK

OGI

14

SELECT EXTERNAL DEVICE

GO

40

LEI

8

ENABLE SHIFT REGISTER

OUTPUT

JP

SEND2

SEND1

XAS

SEND2

LD

DATA TRANSMISSION LOOP

XIS

TURN-ON CLOCK

JP

SEND1

XAS

SEND LAST DATA

RC

WAIT 4 CYCLES - DATA

GOING OUT

CLRA

NOP

XAS

TURN SK CLOCK OFF

OGI

15

DE-SELECT DEVICE

LEI

0

SET S0 TO 0

RET

11