LM3211 datasheet(17/21 Pages) NSC

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Operation (Continued)

LAYOUT CONSIDERATIONS

The LM3211 uses two separate ground connections, GND

for the driver and NMOS power device of the boost regulator

and AGND for the sensitive analog control circuitry of the

boost regulator and the V

COM and Gamma buffers. The

AGND and GND pins should be tied directly together at the

package, see Figure 3 and Figure 4. The feedback, softstart,

and compensation networks should be connected directly to

a dedicated analog ground plane and this ground plane must

connect to the AGND pin, as in Figure 3. If no analog ground

plane is available then the ground connections of the feed-

back, softstart, and compensation networks must tie directly

to the AGND pin, as show in Figure 4. Connecting these

networks to the GND pin can inject noise into the system and

effect performance. For 600kHz operation the FSLCT pin

should be tied to an analog ground plane or directly to the

AGND pin. For 1.25MHz operation the FSLCT pin should be

tied to the V

IN pin.

The input bypass capacitor C

IN must be placed close to the

IC. This will reduce copper trace resistance which effects

input voltage ripple of the IC. For additional input voltage

filtering, a 100nF bypass capacitor can be placed in parallel

with C

IN, close to the VIN pin, to shunt any high frequency

noise to ground. The output capacitor, C

OUT, should also be

placed close to the IC. Any copper trace connections for the

OUT capacitor can increase the series resistance, which

directly effects output voltage ripple and efficiency. The feed-

back network, resistors R1 and R2, should be kept close to

the FB pin, and away from the inductor, to minimize copper

trace connections that can inject noise into the system.

Trace connections made to the inductor and schottky diode

should be minimized to reduce power dissipation and in-

crease overall efficiency.

The layout of the Gamma buffer traces is important to mini-

mize noise injected into them. Route all input and output

traces for the buffers away from the inductor and the high

power switching traces used for the boost switcher. For best

performance route these traces on the opposite side of the

board from the high current switching traces and use a

ground plane between the two sides for shielding.

20062252

FIGURE 3. Multi-Layer Layout

20062253

FIGURE 4. Single Layer Layout

LM3211 Datasheet(PDF) 17 Page - National Semiconductor (TI)

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