TST2 datasheet(3/19 Pages) AKM

3 / 19 page

ASAHI KASEI

[AK5352]

0155-E-00

1997/1

- 3 -

PIN/FUNCTION

No.

Pin Name

I/O

FUNCTION

AINR+

Right channel analog positive input pin

AINR-

Right channel analog negative input pin

VREF

Voltage Reference output pin

(VA-2.6V)

Normally connected to VA with a 0.1uF ceramic capacitor in

parallel with a 10uF electrolytic capacitor.

Analog section Analog Power Supply, +5V

AGND

Analog section Analog Ground

AINL+

Left channel analog positive input pin

AINL-

Left channel analog negative input pin

TST1

TST2

TST3

TST4

Test pin

(Pull-down pin)

Should be left floating.

HPFE

High Pass Filter Enable pin

(Pull-up pin)

"H": ON

"L": OFF

Digital section Digital Power Supply pin, +5V

DGND

Digital section Digital Ground pin

Power Down pin

"L" brings the device into power-down mode. Must be done

once after power-on.

MCLK

Master Clock input pin

CMODE="H" : 384fs

CMODE="L" : 256fs

SCLK

I/O

Serial Data Clock pin

Data is clocked out at the falling edge of SCLK.

Slave mode: 64fs clock is input usually.

Master mode: SCLK outputs a 64fs clock.

SCLK stays low during the power-down mode(PD="L").

LRCK

I/O

L/R Channel Clock Select pin

Slave mode: An fs clock is fed to this LRCK pin.

Master mode: LRCK output an fs clock.

LRCK goes "H" at SMODE2="L" and "L" at SMODE2="H"

during reset when SMODE1 "H".

FSYNC

I/O

Frame Synchronization Signal pin

Slave mode: When "H", data bits are clocked out on SDATA.

As I

2S slave mode ignores FSYNC, it should hold "L" or

"H".

Master mode: FSYNC outputs 2fs clock.

Stay low during the power-down mode(PD="L").

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