ASAHI KASEI

[AK5352]

0155-E-00

1997/1

- 9 -

(Ta=25

Parameter

Symbol

min

typ

max

Unit

Control Clock Frequency

Master Clock

256fs: (fs =

Pulse width Low

Pulse width High

384fs: (fs =

Pulse width Low

Pulse width High

Serial Data Output Clock

Channel Select Clock(Sampling Frequency)

Duty Cycle

4.096

15.9

15.9

6.144

20.83

20.83

16

25

12.288

18.432

3.072

48

25.088

20.736

6.144

98

75

MHz

ns

ns

MHz

ns

ns

MHz

kHz

%

Serial Interface Timing

(Note 18 )

Slave Mode(SMODE1="L")

SCLK Period

SCLK Pulse width Low

Pulse width High

SCLK Rising to LRCK Edge

(Note 19 )

LRCK Edge to SCLK Rising

(Note 19 )

LRCK Edge to SDATA MSB Valid

SCLK Falling to SDATA Valid

SCLK Rising to FSYNC Edge (Note 19 )

FSYNC Edge to SCLK Rising (Note 19 )

Master Mode(SMODE1="H")

SCLK Frequency

Duty Cycle

FSYNC Frequency

Duty Cycle

SCLK Falling to LRCK Edge

LRCK Edge to FSYNC Rising

SCLK Falling to SDATA Valid

SCLK Falling to FSYNC Edge

159.4

65

65

30

30

30

30

-20

-20

64fs

50

2fs

50

1

50

50

20

50

20

ns

ns

ns

ns

ns

ns

ns

ns

ns

Hz

%

Hz

%

ns

tslk

ns

ns

Power down timing

(Note 20 )

150

516

ns

1/fs

Note 18 : Refer to Serial Data Interface.

Note 19 : Specified LRCK and FSYNC edges not to coincide with the rising edges of SCLK.

Note 20 : The number of LRCK rising edges after PD brought high. The value is in master mode.

In slave mode it becomes one LRCK clock(1/fs) longer.