ASAHI KASEI

[AK5352]

0155-E-00

1997/1

- 12 -

Audio Serial Interface has four kinds of mode, it can be changed by SMODE1 and SMODE2 pins. Data format

is MSB first, 2's complement.

Figure

SMODE1

SMODE2

Mode

L/R polarity

Figure 1

L

L

Slave Mode: 20bit, MSB justified

Lch=H, Rch=L

Figure 2

H

L

Master Mode: Similar to I

Figure 3

L

H

Slave Mode: I

Figure 4

H

H

Master Mode: I

Table 2 . Serial Interface

1) SLAVE mode

An output channel is defined by LRCK. Both channel data are output in sequence, in order of the Lch first then

Rch at the rate of fs. Data bits are clocked out via the SDATA pin at SCLK rate. Figure 1 and Figure 3 shows

data output timing at SCLK=64fs. FSYNC enables SCLK to start clocking out data. The MSB is clocked out by

the LRCK edge. SCLK causes the ADC to output succeeding bits when FSYNC is high. However, as I

mode ignores FSYNC, it should hold "L" or "H".

2) MASTER mode

In MASTER mode, the A/D converter is driven from a master clock(MCLK:256fs/384fs) and outputs all other

clocks(LRCK, SCLK). The falling edge of SCLK causes the ADC to output each bit. Figure 2 and Figure 4

shows the output timing. 2x fs clock of 50% duty is output via the FSYNC pin. FSYNC rises one SCLK cycle

during FSYNC "H", lower 4 bit is output after FSYNC "L" transition.

Figure 1 . Data Output Timing (Slave mode)