ASAHI KASEI

[AK5352]

0155-E-00

1997/1

- 16 -

The AK5352 requires careful attention to power supply and grounding arrangements. The VA and VB are

connected together through the chip substrate and have several ohm resistance. The power to VB should

come up at the same time or faster than the power to VD, when they are fed separately to the device (Figure 5 ).

As to the connections of decoupling capacitors, refer to Figure 5 . The 0.1uF of decoupling capacitors

connected power supply pins should be as near as possible to the power supply pin.

As AINL± pins is near VD pin, ground pattern should be inserted between VD line and AINL±lines to avoid

digital noise coupling. Refer to evaluation board manual of AKD5352/1 Rev.B about board layout.

Analog signal is differentially input into the modulator via the AIN+ and the AIN- pins. The input voltage is the

difference between AIN+ and AIN- pins. The full-scale of each pin is ±3.47Vp-p on its reference

voltage(VREF). In case that the positive input is more than its full-scale, the AK5352 outputs positive

7FFFFH(Hex, Full-scale). In case that the negative input is more than its full-scale, the AK5352 outputs

negative 80000H(Hex, Full- scale). In case of an ideal value of no input, outputs 00000H(@20bit). DC offset is

removed by internal HPF.

AK5352 samples the analog inputs at 3.072MHz with fs=48kHz. The digital filter rejects all noise between

26.5kHz and 3.0455MHz. However, the filter will not reject frequencies right around 3.072MHz ( and multiples

of 3.072MHz). Most audio signals do not have significant noise energy at 3.072MHz. Hence, a simple RC filter

is sufficient to attenuate any noise energy at 3.072MHz.

The reference voltage for A/D converter is supplied from the VREF pin at VA reference. In order to eliminate

the effects of high frequency noise on the VREF pin, a 10uF or less electrolytic capacitor and a 0.1uF ceramic

capacitor should be connected parallel between the VREF and the VA pins. No current should be driven from

the VREF pin.

The AK5352 accepts +5V supply voltage. Any voltage which exceeds the upper limit of (VA+)+0.3V and lower

limit of AGND-0.3V and any current beyond 10mA for the analog input pins(AINL±, AINR±) should be avoided.

Excessive currents to the input pins may damage the device. Hence input pins must be protected from signals

at or beyond these limits.

Use caution specially in case of using ±15V in surrounding analog circuit.

To minimize digital originated noise, connect the ADC digital outputs only to CMOS inputs. Logic families of

4000B, 74HC, 74AC, 74ACT and 74HCT series are suitable.

In systems where multiple ADC's are required, care must be taken to insure the internal clocks are synchronized

between converters to make simultaneous sampling. In slave mode, synchronous sampling is achieved by supplying

the same MCLK and LRCK to all converters. In master mode, the same PD signal is supplied to each ADC.The PD

state is released at the first rising edge of MCLK after bringing PD into high. Hence, if the rising edge of PD and rising

edge of MCLK coincides together the sampling difference among the ADC's modulator would occur. The difference

could be 1/256fs in the sampling clock(64fs) of the modulator, typically 81ns at fs=48kHz.