Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

DIGITAL INTERFACE (DATA, CLK, LE, EN, F

I

IH

High-Level Input Current

V

−1.0

1.0

µA

I

IL

Low-Level Input Current

V

−1.0

1.0

µA

I

IH

Oscillator Input Current

V

100

µA

I

IL

Oscillator Input Current

V

−100

µA

V

OH

High-Level Output Voltage

I

V

0.4

V

V

OL

Low-Level Output Voltage

I

0.4

V

MICROWIRE TIMING

t

CS

Data to Clock Setup Time

See Data Input Timing

50

ns

t

CH

Data to Clock Hold Time

See Data Input Timing

10

ns

t

CWH

Clock Pulse Width High

See Data Input Timing

50

ns

t

CWL

Clock Pulse Width Low

See Data Input Timing

50

ns

t

ES

Clock to Load Enable Setup

Time

See Data Input Timing

50

ns

t

EW

Load Enable Pulse Width

See Data Input Timing

50

ns

Note 3: Minimum operating frequencies are not production tested — only characterized.

1.0 Functional Description

The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthesizer

such as the National Semiconductor LMX2353, a voltage controlled oscillator (VCO), and a passive loop filter. The frequency syn-

thesizer includes a phase detector, current mode charge pump, as well as programmable reference [R] and feedback [N] fre-

quency dividers. The VCO frequency is established by dividing the crystal reference signal down via the R counter to obtain a fre-

quency that sets the comparison frequency. This reference signal, fr, is then presented to the input of a phase/frequency detector

and compared with another signal, fp, the feedback signal, which was obtained by dividing the VCO frequency down by way of

the N counter and fractional circuitry. The phase/frequency detector’s current source outputs pump charge into the loop filter,

which then converts the charge into the VCO’s control voltage. The phase/frequency comparator’s function is to adjust the voltage

presented to the VCO until the feedback signal’s frequency (and phase) match that of the reference signal. When this “phase-

locked” condition exists, the RF VCO’s frequency will be N+F times that of the comparison frequency, where N is the integer di-

vide ratio and F is the fractional component. The fractional synthesis allows the phase detector frequency to be increased while

maintaining the same frequency step size for channel selection. The division value N is thereby reduced giving a lower phase

noise referred to the phase detector input, and the comparison frequency is increased allowing faster switching times.

1.1 REFERENCE OSCILLATOR INPUT

The reference oscillator frequency for the PLL is provided by an external reference TCXO through the OSC

operate to 50 MHz with a minimum input sensitivity of 0.5 V

an external CMOS or TTL logic gate.

1.2 REFERENCE DIVIDER (R-COUNTER)

The R-counter is clocked through the oscillator block. The maximum frequency is 50 MHz. The R-counter is CMOS design and

15-bit in length with programmable divider ratio from 3 to 32,767.

1.3 FEEDBACK DIVIDER (N-COUNTER)

The N counter is clocked by the small signal f

The integer part is configured as a 5-bit A counter and a 10-bit B counter. The LMX2353 is capable of operating from 500 MHz

to 1.2 GHz with the 16/17 prescaler offering a continuous integer divide range from 272 to 16399, and 1.2 GHz to 2.5 GHz with

the 32/33 prescaler offering a continuous integer divide range from 1056 to 32767. The fractional compensation is programmable

in either 1/15 or 1/16 modes.

1.3.1 Prescaler

The RF input to the prescaler consist of f

mentary input is internally coupled to ground with a 10 pF capacitor. This input is typically AC coupled to ground through external

capacitors as well. A 16/17 or 32/33 prescaler ratio can be selected.

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