1.10 POWER CONTROL

The PLL is power controlled by the device enable pin (CE) or MICROWIRE power down bit. The enable pin overrides the power

down bit

except for the V2_EN bit. When CE is high, the power down bit determines the state of power control. Activation of any

PLL power down mode results in the disabling of the N counter and de-biasing of f

counter functionality also becomes disabled when the power down bit is activated. The reference oscillator block powers down

and the OSCin pin reverts to a high impedance state when CE or power down bit’s are asserted,

unless the V2_EN bit (R[20])

is high. Power down forces the charge pump and phase comparator logic to a TRI-STATE condition. A power down counter reset

function resets both N and R counters. Upon powering up the N counter resumes counting in “close” alignment with the R counter

(The maximum error is one prescaler cycle). The MICROWIRE control register remains active and capable of loading and latching

in data during all of the power down modes.

2.0 Programming Description

2.1 MICROWIRE INTERFACE

The LMX2353 register set can be accessed through the MICROWIRE interface. A 24-bit shift register is used as a temporary reg-

ister to indirectly program the on-chip registers. The shift register consists of a 24-bit DATA[21:0] field and a 2-bit ADDRESS[1:0]

field as shown below. The address field is used to decode the internal register address. Data is clocked into the shift register in

the direction from MSB to LSB, when the CLOCK signal goes high. On the rising edge of Latch Enable (LE) signal, data stored

in the shift register is loaded into the addressed latch.

MSB

LSB

DATA[21:0]

ADDRESS[1:0]

23

2

1

0

2.1.1 Registers’ Address Map

When Latch Enable (LE) is transitioned high, data is transferred from the 24-bit shift register into the appropriate latch depending

on the state of the ADDRESS[1:0] bits. A multiplexing circuit decodes these address bits and writes the data field to the corre-

sponding internal register.

ADDRESS[1:0]

FIELD

REGISTER

ADDRESSED

0

0

F1 Register

0

1

F2 Register

1

0

R Register

1

1

N Register

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