2.2 R REGISTER

If the ADDRESS[1:0] field is set to 1 0 data is transferred from the 24-bit shift register into the R register which sets the PLL’ s

15-bit R-counter divide ratio when Latch Enable (LE) signal goes high. The divide ratio is put into the R_CNTR[14:0] field and is

described in section 2.2.1. The divider ratio must be

≥ 3. The bits used to control the voltage doubler (V2_EN), Delay Lock Loop,

(DLL_MODE), Charge Pump (CP_WORD) are detailed in section 2.2.2 -2.2.4 below.

Most Significant Bit

SHIFT REGISTER BIT LOCATION

Least Significant Bit

23

22

21

20

19

18

17

16

15

14

13

12

11 10

987654

3

2

1

0

Data Field

Address Field

DLL_

MODE

V2_

EN

CP_WORD[4:0]

R_CNTR[14:0]

10

R

_21

R

_20

R

_19

R

_18

R

_17

R

_16

R

_15

R

_14

R

_13

R

_12

R

_11

R

_10

R

_9

R

_8

R

_7

R

_6

R

_5

R

_4

R

_3

R

_2

R

_1

R

_0

2.2.1 Reference Divide Ratio

(R_CNTR)

If the ADDRESS[1:0] field is set to 1 0 data is transferred MSB first from the 24-bit shift register into a latch which sets the 15-bit

R Counter, R_CNTR[14:0]. Serial data format is shown below.

R_CNTR[14:0]

Divide Ratio

R_14 R_13 R_12 R_11 R_10

R_9

R_8

R_7

R_6

R_5

R_4

R_3

R_2

R_1

R_0

3

000000000000011

4

000000000000100

•

•••••••••••••••

32,767

111111111111111

Note: R-counter divide ratio must be from 3 to 32,767.

2.2.2 V2_EN

(R_20)

The V2_EN bit when set high enables the voltage doubler for the charge pump supply.

Bit

Location

Function

0

1

V2_EN

R_20

Voltage Doubler Enable

Disable

Enabled

2.2.3 DLL_MODE

(R_21)

The DLL_MODE bit should be set to 1 for normal usage.

Bit

Location

Function

0

1

DLL_MODE

R_21

Delay Line Loop

Calibration Mode

Slow

Fast

2.2.4 CP_WORD

(R_15-R_19)

R_19

R_18

R_17

R_16

R_15

CP_8X

CP_4X

CP_2X

CP_1X

PD_POL

2.2.4.1 Charge Pump Output Truth Table

ICP

R_19

R_18

R_17

R_16

CP_8X

CP_4X

CP_2X

CP_1X

100

0000

200

0001

300

0010

400

0011

-

----

900

1000

-

----

1600

1111

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