2.3.2.4 Power Down Mode

(PWDN_MODE)

Synchronous Power Down Mode

The PLL loop can be synchronously powered down by setting the PWDN mode bit HIGH (F2_19=1) and then asserting the power

down mode bit (N20 = 1). The power down function is gated by the charge pump. Once the power down program bit is loaded,

the part will go into power down mode upon the completion of a charge pump pulse event.

Asynchronous Power Down Mode

The PLL loop can be asynchronously powered down by setting the PWDN mode bit LOW (F2_19=0) and then asserting the

power down mode bit (N20 = 1). The power down function is NOT gated by the charge pump. Once the power down program bit

is loaded, the part will go into power down mode immediately.

2.3.3 Feedback Divide Ratio

(NB Counter)

NB_CNTR[9:0]

Divide Ratio

N_18

N_17

N_16

N_15

N_14

N_13

N_12

N_11

N_10

N_9

3

000000001

1

4

000000010

0

•

•••••••••

•

1023

111111111

1

Note: B-counter divide ratio must be

≥ 3.

NB_CNTR

≥ (NA_CNTR +2).

2.3.4 Swallow Counter Divide Ratio

(NA Counter)

NB_CNTR[4:0]

Divide Ratio

N_8

N_7

N_6

N_5

N_4

0

00000

1

00001

•

•••••

31

11111

Note: Swallow Counter Value: 0 to 31.

NB_CNTR

≥ (NA_CNTR +2).

2.3.5 Fractional Modulus Accumulator

(FRAC_CNTR)

Divide

Ratio

Divide

Ratio

FRAC_CNTR[3:0]

Modulus 15

Modulus 16

N_3

N_2

N_1

N_0

0

0

0000

1/15

1/16

0001

2/15

2/16

0010

•

•

••••

14/15

14/16

1110

N/A

15/16

1111

2.3.6 Pulse Swallow Function

f

f

Output frequency of external voltage controlled oscillator (VCO)

F:

Fractional ratio (contents of FRAC_CNTR divided by the fractional modulus)

B:

Preset divide ratio of binary 10-bit programmable counter (3 to 1023)

A:

Preset divide ratio of binary 5-bit swallow counter

f

Output frequency of the external reference frequency oscillator

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