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TAS5076 Datasheet(PDF) 51 Page - Texas Instruments |
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TAS5076 Datasheet(HTML) 51 Page - Texas Instruments |
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51 / 62 page ![]() Specifications 45 SLES090A—November 2003—Revised January 2004 TAS5076 tsu(LRCLK) SCLK LRCLK NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns). Figure 5−7. Right, Left, and I2S Serial Mode Timing Requirement LRCLK SCLK MCLK t(MRLD) t(MSD) Figure 5−8. Serial Audio Ports Master Mode Timing LRCLK SCLK SDIN tsu(LRCLK) th(SDIN) th(LRCLK) tw(FSHIGH) tsu(SDIN) Figure 5−9. DSP Serial Port Timing |
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