TAS5076 datasheet(30/62 Pages) TI

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Architecture Overview

SLES090A—November 2003—Revised January 2004

TAS5076

2.5.1 Single-Byte Write

As shown in Figure 2−14, a single-byte data write transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction

of the data transfer. For a write data transfer, the read/write bit is 0. After receiving the correct I2C device

address and the read/write bit, the TAS5076 device responds with an acknowledge bit. Next, the master

transmits the address byte or bytes corresponding to the TAS5076 internal memory address being accessed.

After receiving the address byte, the TAS5076 again responds with an acknowledge bit. Next, the master

device transmits the data byte to be written to the memory address being accessed. After receiving the data

byte, the TAS5076 again responds with an acknowledge bit. Finally, the master device transmits a stop

condition to complete the single-byte data write transfer.

R/W ACK A7

ACK

Stop

Condition

Acknowledge

I2C Device Address and

Read/Write Bit

Data Byte

Start

Condition

Figure 2−14. Single-Byte Write Transfer

2.5.2 Multiple-Byte Write

A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes

are transmitted by the master device to TAS5076 as shown in Figure 2−15. After receiving each data byte,

the TAS5076 responds with an acknowledge bit.

D0 ACK

Stop

Condition

Acknowledge

I2C Device Address and

Read/Write Bit

Last Data Byte

R/W ACK A7

ACK D7

D0 ACK

Start

Condition

Acknowledge

First Data Byte

Other

Data Bytes

Figure 2−15. Multiple-Byte Write Transfer

2.5.3 Single-Byte Read

As shown in Figure 2−16, a single-byte data read transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. For the data read transfer, a write followed

by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory

address to be read. As a result, the read/write bit is 0. After receiving the TAS5076 address and the read/write

bit, the TAS5076 responds with an acknowledge bit. Also, after sending the internal memory address byte or

bytes, the master device transmits another start condition followed by the TAS5076 address and the read/write

bit again. This time the read/write bit is a 1 indicating a read transfer. After receiving the TAS5076 and the

read/write bit, the TAS5076 again responds with an acknowledge bit. Next, the TAS5076 transmits the data

byte from the memory address being read. After receiving the data byte, the master device transmits a not

acknowledge followed by a stop condition to complete the single-byte data read transfer.

R/W ACK A7

A0 ACK

ACK

Start

Condition

Stop

Condition

Acknowledge

I2C Device Address and

Read/Write Bit

Data Byte

D0 ACK

I2C Device Address and

Read/Write Bit

Repeat Start Condition

Not

Acknowledge

R/W

Figure 2−16. Single-Byte Read

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