TLC34076 datasheet(38/68 Pages) TI

38 / 68 page

2–22

Sampled

LOAD

Input

SFLAG/NFLAG

of Pixel Data

Latch First Group

of Pixel Data

Latch Last Group

Valid

Don’t Care

Valid

(at its input pin)

Last Group of Pixel Data

SCLK

PIXEL DATA

BLANK

VCLK

NOTES: A. If the data is not held valid until SCLK and BLANK both go low, the last few pixels could be missed.

B. Setup time to the next VCLK falling edge after BLANK goes high must be met; otherwise, the first

pixel data could be missed.

Group

2nd

Group

1st

Group

4th

Group

3rd

Group

5th

(see Note A)

(see Note B)

Figure 2–10. SFLAG/NFLAG Timing in Special Nibble Mode

Special nibble mode operates at the line frequency when BLANK is active. However, the typical application

of this mode is double frame buffers with pixel data width of 4 bits. While one frame buffer is being displayed

on the monitor, the other frame buffer can accept new picture information. SFLAG/NFLAG indicates which

frame buffer is being displayed.

SNM and SSRT must be mutually exclusive. Unpredictable operation occurs when both the SNM and SSRT

bits are set to 1. The mux control register should be set up as shown in Table 2– 6. However, the SNM bit

takes precedence over the other mux control register selections. In other words, when the mux control

the input multiplex circuit takes whatever SCLK divide ratio the mux control register specifies and performs

the nibble operation causing operational failure.

During special nibble mode, the input mux circuit latches all 8-bit inputs but only passes on the specified

nibble. The specified nibble is stored in the four LSBs of the next register pipe after the input latch, and the

four MSBs are cleared to 0 in that register. The register pipe contents are then passed to the read mask

block. With this structure, the palette page register still functions normally, providing good flexibility to users.

When the general control register bit 3 = 0 and bit 2 = 0, both split shift-register transfers and the special

nibble mode are disabled and the SFLAG/NFLAG input is ignored.

TLC34076 Datasheet(PDF) 38 Page - Texas Instruments

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