TLC34076 datasheet(21/68 Pages) TI

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2–5

2.3.1

SCLK

Data is latched inside the device on the rising edge of LOAD, which is basically the same as SCLK but not

disabled during Blank active period. Therefore, SCLK must be set as a function of the pixel bus width and

the number of bit planes. SCLK can be selected as 1, 2, 4, 8, 16, or 32 divisions of the dot clock. When SCLK

is not used, the output is switched off and held low to protect against VRAM lock-up due to invalid SCLK

frequencies. SCLK is also held low during the Blank active period. The SCLK control timing has been

designed to interface directly with the external system VRAM. The shift register in the system VRAM should

be updated during the Blank active period. This allows the first SCLK out of Blank to clock the VRAM and

enable the first group of pixel data to appear on the pixel bus, as well as at the TLC34076 pixel input port.

The second SCLK after Blank latches the first group of pixel port data into the TLC34076.

The trailing edge of VCLK is used internally by the TLC34076 to sample and latch the BLANK input. When

BLANK becomes active, SCLK is disabled as soon as possible. For example, when SCLK is high and the

sampled BLANK goes low, SCLK is allowed to complete the clock cycle and return to the low state. SCLK

is then held low until the sampled BLANK signal goes high. At this time, SCLK is enabled to clock the VRAM

again. The TLC34076 video blanking circuitry is designed with sufficient pipeline delay to allow the internally

sampled BLANK signal to align with the pipelined RGB data to the video DACs. The logic described herein

works in situations where the SCLK period is shorter than, equal to, or longer than the VCLK period.

When the VRAM split shift-register operation is performed, the SCLK timing is adjusted to work with the

SFLAG input. Basically, the split shift register operation inserts a SCLK during the Blank period. This causes

the first group of pixel data to appear at the pixel port during the Blank signal. The first SCLK after Blank

then latches this data into the TLC34076. Figure 2–3 shows the case when the split shift register transfer

(SSRT) function is enabled. When a rising edge occurs on the SFLAG input, one SCLK with a minimum of

15-ns pulse duration is generated after the specified delay. Since this is designed to meet VRAM timing

requirements, the SSRT-generated SCLK replaces the first SCLK in the regular shift register transfer case

as previously described (see to Section 2.9 for a detailed explanation of the SSRT function).

The default divide ratio for SCLK is 1:1 as used in mode 0.

Depending on the frequency relationship between SCLK and VCLK, their phase relationship could be critical

(see Appendix C for a more detailed discussion).

TLC34076 Datasheet(PDF) 21 Page - Texas Instruments